Tag
address-translation
- Oct 4, 2026 Non-Transparent Bridges and Multi-Host PCIe Topologies Why two root complexes cannot simply be cabled together, how a non-transparent bridge presents a translated address window to each side, and what the doorbell handshake does not guarantee. hardware engineering
- May 1, 2026 Internet Gateway, NAT, and Source Address Translation How a VPC reaches the public internet without exposing private addresses, why a NAT gateway is one-way, and how the translation table interacts with connection tracking and path MTU discovery. cloud infrastructure
- Feb 9, 2026 Address Translation Across Host and Device A GPU access may traverse three translation stages, and where the stages live determines whether a shared address space is cheap, whether faults are recoverable, and what a migration can move. gpu computing
- Feb 1, 2026 Nested Paging: Two-Dimensional Translation for Virtual Machines How a guest physical address becomes a host physical address, why the walk cost multiplies, and which workloads suffer most from the second level of tables. memory systems
- Dec 17, 2025 Device DMA and the IOMMU Boundary What a device must be given before it can write to host memory, how an IOMMU turns a device address into a machine address, and what that translation costs. computer architecture
- Nov 4, 2025 Walking a Multi-Level Page Table How four levels of tables turn a 36-bit page number into a frame, what each level costs in memory and cache misses, and why the walk is not free even when it succeeds. memory systems
- Aug 17, 2025 Splitting a Virtual Address into Page Number and Offset Why translation happens at page granularity, how the address bits divide between frame number and offset, and what that division costs in fragmentation and alignment. memory systems
- May 22, 2025 Dynamic Address Translation and the 16 MB Line How a two-level segment and page table turns a 24-bit virtual address into a real one, why the page tables themselves had to live in real storage, and what the 16 MB ceiling forced. computing history
- May 6, 2025 Second-Level Address Translation: Composing Two Page Walks in Hardware How EPT and nested paging remove the shadow-table trap per guest page-table write, what the extra walk costs in memory references, and why accessed and dirty bits become a virtualization problem. virtualization
- May 6, 2025 The TLB, Associativity, and What a Miss Actually Costs How the translation cache is organised, why it is small and fully associative, what the hardware does on a miss, and which access patterns destroy its hit rate. memory systems
- May 25, 2024 Kernel Page Table Isolation and What It Costs on Every Trap Why splitting the kernel into a separate address space defends against speculative reads, how the switch is arranged to be nearly free, and where the remaining cost lands. memory systems
- Apr 17, 2024 Virtually Indexed Caches and the Page Coloring Problem Why a cache can start its lookup from a virtual address and finish with a physical tag, when that creates synonyms, and how page coloring controls which sets a process occupies. memory systems
- Jul 6, 2023 Device DMA Addressing and What the IOMMU Changes How a device names memory without access to the CPU page tables, why 32-bit DMA needs bounce buffers, and how an IOMMU translates device addresses per requester. hardware engineering