Tag
clocking
- May 5, 2025 Clock Networks, Global Buffers, and Skew Budgets Why a clock reaches every register through a dedicated balanced tree, what skew and jitter cost a timing budget, and when a clock must be routed on general interconnect instead. hardware engineering
- Nov 12, 2024 Latches, Flip-Flops, and What Edge Sensitivity Actually Means How a cross-coupled pair stores a bit, why a master-slave arrangement turns level sensitivity into edge triggering, and what transparency costs downstream. hardware engineering