Tag
dma
- Oct 12, 2026 Bus Matrix Arbitration and What DMA Contention Costs the Core How a multi-master bus fabric picks a winner when the core and a DMA engine target the same SRAM, why round-robin is not always fair, and how contention shows up as jitter. embedded systems
- Apr 19, 2026 Pinned Host Memory and Why Pageable Transfers Cannot Be Asynchronous Why a copy engine cannot be handed an ordinary host pointer, what the driver does instead, and how the staging buffer turns an asynchronous copy into a synchronous one. gpu computing
- Apr 9, 2026 Channel Programs: How a Mainframe Moved Data Without the CPU The command word format a channel executes, how chaining turns a list of commands into one operation, and why the channel is a separate processor rather than a DMA engine. computing history
- Mar 30, 2026 Peripheral Clock Gating and Autonomous Transfer How gating a peripheral clock saves dynamic power, why a gated peripheral still costs leakage, and how DMA lets a conversion happen with the core asleep. embedded systems
- Mar 25, 2026 Host-Device Transfers and the Cost of Crossing the Bus Pinned versus pageable host memory, why a blocking copy costs more than its bandwidth suggests, and where the staging copy inside the runtime comes from. gpu computing
- Feb 1, 2026 The Virtio Split Ring: Descriptor Chaining and the Two Suppression Flags The byte layout of the descriptor table, available ring, and used ring, how descriptors chain through guest memory, and how the event-index mechanism replaces the older no-notify flags. virtualization
- Dec 17, 2025 Device DMA and the IOMMU Boundary What a device must be given before it can write to host memory, how an IOMMU turns a device address into a machine address, and what that translation costs. computer architecture
- Oct 10, 2024 The Interception Surface of a Virtual GPU A GPU presents a register file, a bus-mastering DMA engine, and an interrupt source at once; sharing one means deciding which of the three the host keeps control of. gpu computing
- Sep 16, 2024 Descriptor Rings and the Producer-Consumer Contract How a ring buffer carries work from a driver to a device without locks, what the ownership bit buys, and why the wrap-around index is the hard part. computer architecture
- Aug 28, 2023 Ordering Across the Device Boundary: DMA, MMIO, and Posted Writes Why a device can read stale data after a synchronising store, how posted writes hide completion, and which barriers cross the boundary in each direction. computer architecture
- Jul 6, 2023 Device DMA Addressing and What the IOMMU Changes How a device names memory without access to the CPU page tables, why 32-bit DMA needs bounce buffers, and how an IOMMU translates device addresses per requester. hardware engineering
- Jun 10, 2023 Counting Copies on the Virtual I/O Path: Userspace, vhost, and Passthrough How many times a packet is touched between a guest buffer and the wire in each device model, what each eliminated copy costs in complexity, and where the remaining copies cannot be removed. virtualization