Tag
instruction-encoding
- Aug 24, 2026 Register Windows and Why Explicit Operand Registers Won How register window architectures eliminate spill code on call, what the window management traps cost, and why load-store ISAs settled on flat register files with fixed fields. computer architecture
- Jul 20, 2026 Stack Machines and Register Machines as Bytecode Targets Why bytecode formats choose implicit stack operands or named registers, and what that choice costs in encoding width, instruction count, and verifier complexity. language runtimes
- Jul 2, 2026 Immediate Encoding and How Arbitrary Constants Get Materialized Why an instruction can hold only a small constant, how sign extension and scaled fields are packed into the word, and the instruction sequences that build a full-width value. computer architecture
- Feb 22, 2026 Two-Operand Encodings and the Destructive Write Problem Why the second source register disappears in a two-operand format, how destructive writes constrain register allocation, and what a three-operand format buys back. computer architecture
- Nov 24, 2025 Fixed-Width Instruction Encoding and Where the Fields Go How a 32-bit instruction divides into opcode, register and immediate fields, why the register fields keep the same bit offsets across formats, and what that costs in reachable constants. computer architecture
- Oct 26, 2025 Fixed-Width SIMD Lanes Versus Scalable Vector Registers Why one design bakes the vector length into the instruction encoding and the other reports it at run time, and how each choice propagates into code generation, binary compatibility, and register pressure. computer architecture
- Oct 24, 2025 Opcode Space Allocation and How Extensions Claim Encodings How an instruction set divides its opcode map among base operations, extensions and vendor additions, and what happens when the map runs out of room. computer architecture
- Mar 20, 2025 Constant Pools and Operand Encoding in Bytecode Why bytecode instructions reference large constants indirectly through a pool, how the pool is laid out, and what the fixed-width index fields cost. language runtimes
- Mar 20, 2025 Zero Page Addressing and the Economics of Eight-Bit Instructions Placing the first 256 bytes of memory at the centre of the instruction set traded address range for instruction length, and shaped how eight-bit code was written. computing history
- Sep 12, 2024 Addressing Modes and How an Effective Address Is Computed How base, index, scale and displacement fields combine into an address, why some ISAs fold memory operands into arithmetic, and what each mode costs in the datapath. computer architecture
- Jul 10, 2024 VLIW Bundles and the Compiler as Scheduler How very long instruction word machines move dependence checking and slot assignment into the compiler, what that buys in hardware, and why exposed pipeline latency and binary compatibility make the trade expensive. computer architecture
- May 31, 2024 Condition Codes, Flag Registers and the Dependency They Create How comparison results become flags, why an implicit flag register serialises code, and how architectures that compare directly into registers avoid the hazard. computer architecture
- Mar 24, 2024 SIMD Encoding: Vector Register Fields, Predication and Length How vector instructions spend their encoding bits on register numbers, masks and element widths, and why vector length is sometimes in the instruction and sometimes in a control register. computer architecture
- Oct 13, 2023 Instruction Encoding on the Harvard Mark I Paper Tape How a 24-channel tape carries three eight-bit fields per instruction, what the index numbers address, and why a one-way sequence unit made program loops physical. computing history