Tag
instruction-level-parallelism
- Feb 22, 2026 Two-Operand Encodings and the Destructive Write Problem Why the second source register disappears in a two-operand format, how destructive writes constrain register allocation, and what a three-operand format buys back. computer architecture
- Apr 30, 2025 Software Pipelining and Loop-Carried Dependences How modulo scheduling overlaps iterations of a loop, why the recurrence constraint sets a hard lower bound on cycles per iteration, and how unrolling and register pressure limit the schedule. computer architecture
- Dec 24, 2024 Issue Width and the Structural Ceiling on Instructions per Cycle How a superscalar core decides how many instructions to start per cycle, which pipeline stage usually sets the limit, and why a four-wide machine rarely retires four instructions per cycle. computer architecture
- Jul 10, 2024 VLIW Bundles and the Compiler as Scheduler How very long instruction word machines move dependence checking and slot assignment into the compiler, what that buys in hardware, and why exposed pipeline latency and binary compatibility make the trade expensive. computer architecture
- Jun 6, 2023 The Five-Stage Pipeline and the Throughput It Buys Why splitting a datapath into five stages raises instruction throughput without shortening any single instruction, and what latch overhead and stage imbalance take back. computer architecture