Tag
instruction-scheduling
- Sep 14, 2026 Instruction Scheduling and Its Dependence on the Graph How list scheduling trades register pressure against parallelism, what latency and resource tables must contain, and why the scheduler sees a different graph from the one the optimiser built. compilers
- Sep 9, 2026 Scheduling Before Allocation and the Pressure Trade Why an aggressive instruction schedule can force spills that erase its own benefit, how pressure-aware scheduling caps live values, and what iterative repair actually converges on. compilers
- Mar 18, 2026 Loop Unrolling, Trip Counts, and the Cost of Code Growth Unrolling by a known factor removes loop overhead and enables scheduling across iterations, but it needs trip-count knowledge, a remainder loop, and a register-pressure check to pay off. compilers
- Oct 21, 2025 List Scheduling and the Critical Path How a basic-block scheduler orders instructions to hide latency, why the critical path bounds the result, and how register pressure forces it to give that bound up. compilers
- Jan 22, 2025 Bundling Instructions for VLIW Issue Slots How a compiler packs independent operations into fixed-width bundles, why empty slots become explicit no-ops, and how slot assignment and stop bits constrain the scheduler. compilers
- Jul 30, 2024 If-Conversion, Predication, and the Limits of Speculation How conditional branches become data dependences on a predicate, when that is profitable, and why the transformation must respect faults, exceptions, and the register file. compilers
- Apr 8, 2024 Modulo Scheduling and Software Pipelining How a loop is transformed so that successive iterations overlap in the pipeline, what the initiation interval bounds are, and why prologue and epilogue code appears at the edges. compilers
- Jan 30, 2024 Delay Slots and the Burden They Move to the Compiler Why some architectures require the instruction after a branch to execute unconditionally, which instructions are legal in that slot, and what the scheduler must prove before filling it. computer architecture
- Feb 18, 2022 Sea of Nodes: Scheduling Without a Fixed Instruction Order How a graph-based IR represents data, control, and memory dependences as edges with no block order, what scheduling then becomes, and which analyses become harder when nothing is sequential. compilers