Tag
iommu
- May 4, 2026 PCI Passthrough and the Boundaries an IOMMU Actually Draws Why handing a GPU to a guest requires an isolation unit that no sibling device can bypass, and what changes when the device caches its own translations. gpu computing
- Feb 9, 2026 Address Translation Across Host and Device A GPU access may traverse three translation stages, and where the stages live determines whether a shared address space is cheap, whether faults are recoverable, and what a migration can move. gpu computing
- Feb 6, 2026 Virtual Interrupts: APIC Emulation, Interrupt Remapping, and Posted Delivery How a guest programs its own interrupt controller without touching the host's, what the IOMMU must check before a device interrupt is delivered, and why posted interrupts remove the exit from the delivery path. virtualization
- Dec 17, 2025 Device DMA and the IOMMU Boundary What a device must be given before it can write to host memory, how an IOMMU turns a device address into a machine address, and what that translation costs. computer architecture
- Jun 17, 2025 Unified Virtual Addressing and How a Pointer Becomes Usable on a Device Why a single address space spanning host and device memory lets an API infer a pointer location from its value, what that inference depends on, and where it fails. gpu computing
- Jun 1, 2025 Shared Virtual Addressing and Peer-to-Peer Transfers What changes when a device uses the process page table directly, why a PASID is needed, and what must happen before one device writes into another device's memory. computer architecture
- Jul 6, 2023 Device DMA Addressing and What the IOMMU Changes How a device names memory without access to the CPU page tables, why 32-bit DMA needs bounce buffers, and how an IOMMU translates device addresses per requester. hardware engineering