Tag
memory-model
- Sep 30, 2026 Litmus Tests as Executable Specifications How a five-line concurrency test becomes a machine-checkable claim, what the litmus file format encodes, and how a model checker decides which outcomes are forbidden. memory systems
- Jul 12, 2026 Happens-Before, Data Races, and the Memory Model Contract What a memory model promises about reordering, why a data race is undefined rather than merely surprising, and how release and acquire pairs carry a happens-before edge. programming languages
- Apr 3, 2026 System-Scope Atomics and Memory Ordering Across the Bus Why an atomic operation on device memory is not automatically visible to the host, what the scope qualifier changes, and how release and acquire order a flag against its payload. gpu computing
- Mar 16, 2026 Coherence and the Modification Order of a Single Location The four coherence axioms, why per-location agreement is much weaker than a global order, and how IRIW separates the two. memory systems
- Nov 20, 2025 Release, Acquire, and the Synchronizes-With Edge What an acquire load is forbidden to move above, what a release store is forbidden to move below, and why the edge is directional rather than a barrier. memory systems
- Sep 11, 2025 The DRF-SC Guarantee and What It Buys a Programmer Why race-free programs are sequentially consistent on hardware that is not, and the composition rules that let this promise survive layers of abstraction. memory systems
- May 27, 2025 Dependencies, RCsc, and RCpc Acquire on ARMv8 How address and data dependencies order accesses without a barrier, and why ARMv8.3 added a second, cheaper form of acquire load alongside the original one. memory systems
- May 21, 2025 Sequential Consistency as the Reference Memory Model Lamport's two conditions, the executions they exclude, and why every weaker model is described by which of those exclusions it gives up. memory systems
- Apr 10, 2025 The Linux Kernel Memory Model and Its Tooling How LKMM formalises READ_ONCE, smp_mb, and RCU into an executable model, what its relation set adds to the architecture models, and where it deliberately diverges from C11. memory systems
- Nov 1, 2024 Causality and Out-of-Thin-Air Values in the Java Model Why the Java Memory Model needed a causality order rather than happens-before alone, and how the happens-before consistency rules leave room for a value with no writer. memory systems
- Sep 27, 2024 Atomics, Fences, and Memory Scopes in Device Code What a device-scope atomic orders, why relaxed operations reorder across a barrier, and how scope qualifiers change what a fence must flush. gpu computing
- Jun 28, 2024 Store Buffers and the x86-TSO Model How a per-core write buffer leaves store-load as the only program-order pair that may invert, why forbidding it would defeat the buffer, and what a locked instruction orders. memory systems
- Apr 26, 2024 Acquire and Release: What Each Ordering Forbids The precise prohibitions that acquire and release each impose, why the pair cannot order a store against a later load, and when a standalone fence is the only option. systems programming
- Apr 26, 2024 Atomicity and Ordering Are Separate Guarantees in the C Memory Model Why making a shared object atomic removes lost updates but not stale reads, how the C memory model defines a data race, and what happens-before does and does not cover. systems programming
- Feb 24, 2024 Data Race Detection with Vector Clocks and Happens-Before Order How ThreadSanitizer replaces happens-before with vector clocks per memory access, why the shadow word costs eight bytes per four, and where the ordering it assumes is wrong. systems programming
- Oct 27, 2023 Data Races, Memory Models, and Where Parallel Algorithms Lose Determinism How relaxed memory ordering breaks the intuitive interleaving model, what the C and C++ memory model guarantees, and why race-free parallel code can still be non-deterministic. algorithms
- Jul 21, 2023 Litmus Tests and Store Buffering How a five-line litmus test distinguishes total store order from sequential consistency, why the x86 store buffer permits a forbidden outcome, and what each outcome costs to rule out. systems programming
- Mar 18, 2022 Happens-Before and the Definition of a Data Race How sequenced-before and synchronizes-with compose into a partial order, why a race is a pair of unordered conflicting accesses, and what the standard does once one exists. memory systems