Tag

memory-ordering

25 articles

Oct 2, 2026 Propagation, Cumulativity, and Why Weak Models Need Transitive Visibility Messages that preserve ordering are not enough: a store already observed by one thread must be observed by every thread it reaches, and multi-copy atomicity is the property that says so. computer architecture
Sep 20, 2026 Acquire and Release as One-Way Ordering Constraints How a release store and an acquire load each constrain ordering in only one direction, and why the pair is enough to publish data without a full fence. computer architecture
Sep 16, 2026 Posted Writes and the Ordering Rules a Device Must Respect Why PCIe memory writes are fire-and-forget, which transactions may pass which, and how a device orders its data ahead of its interrupt so the handler sees a completed transfer. hardware engineering
Jul 24, 2026 Litmus Tests and How Allowed Outcomes Are Decided How a few lines of concurrent code pin down a memory model, how tools enumerate the executions, and why "never observed" is weaker than "forbidden". computer architecture
Jul 17, 2026 Compiler Reordering and the Contract It Must Not Break Why an optimiser may sink an atomic load past a store only in certain cases, where the as-if rule stops, and how data races turn a performance model into undefined behaviour. computer architecture
Apr 28, 2026 Store Buffers and the Total Store Order That Replaces Sequential Consistency How a per-core store buffer hides cache-miss latency, exactly which four orderings TSO keeps, and why load-load reordering is forbidden while load-store is not. computer architecture
Apr 17, 2026 Cache Coherence Is Per Location, Consistency Is Not Why a machine can agree perfectly on the order of writes to every individual address and still produce an execution with no single global ordering. computer architecture
Apr 3, 2026 System-Scope Atomics and Memory Ordering Across the Bus Why an atomic operation on device memory is not automatically visible to the host, what the scope qualifier changes, and how release and acquire order a flag against its payload. gpu computing
Mar 14, 2026 Seqlocks: Optimistic Reading Without Blocking the Writer How a version counter lets readers copy shared data without registering, why the writer never waits, and which data types make the retry loop impossible to get right. operating systems
Feb 17, 2026 Read-Copy-Update: Publishing New Versions and Waiting Out Old Readers How RCU lets readers run without any synchronization instruction at all, what a grace period must prove before memory can be freed, and where the approach stops working. operating systems
Oct 21, 2025 Acquire and Release Ordering: What a Lock Actually Guarantees About Memory How store buffers and compiler reordering let a consumer observe a published value before the data it points to, and how release and acquire operations restore the ordering without a full fence. operating systems
Sep 15, 2025 What a Fence Instruction Actually Does to the Pipeline The three mechanisms behind fence cost — buffer drain, request acknowledgement, and memory-operation serialisation — and why a fence is never a cache flush. computer architecture
May 21, 2025 Sequential Consistency as the Reference Memory Model Lamport's two conditions, the executions they exclude, and why every weaker model is described by which of those exclusions it gives up. memory systems
Apr 12, 2025 Cacheability, Write-Combining, and Mapping Device Memory How page attributes control caching for MMIO and DMA, what happens when a load is speculatively reordered past a device write, and why the mapping must be uncached. memory systems
Sep 22, 2024 Work-Stealing Deques and Why the Thief Takes the Oldest Task Per-worker deques with LIFO local execution and FIFO stealing keep hot data on one core, and the memory-ordering requirements that make the concurrent deque correct are narrower than they look. language runtimes
May 1, 2024 Seqlocks: Consistent Reads Without Reader-Side Writes How an even/odd sequence counter lets readers detect a concurrent update, why the read side must be free of side effects, and what the retry cost looks like under write-heavy load. systems programming
Apr 26, 2024 Acquire and Release: What Each Ordering Forbids The precise prohibitions that acquire and release each impose, why the pair cannot order a store against a later load, and when a standalone fence is the only option. systems programming
Apr 26, 2024 Atomicity and Ordering Are Separate Guarantees in the C Memory Model Why making a shared object atomic removes lost updates but not stale reads, how the C memory model defines a data race, and what happens-before does and does not cover. systems programming
Jan 22, 2024 Sequential Consistency and the Cost of One Global Memory Order What Lamport's definition of sequential consistency requires of a machine, which reorderings it forbids, and why every commercial processor relaxes it. computer architecture
Oct 27, 2023 Data Races, Memory Models, and Where Parallel Algorithms Lose Determinism How relaxed memory ordering breaks the intuitive interleaving model, what the C and C++ memory model guarantees, and why race-free parallel code can still be non-deterministic. algorithms
Aug 28, 2023 Ordering Across the Device Boundary: DMA, MMIO, and Posted Writes Why a device can read stale data after a synchronising store, how posted writes hide completion, and which barriers cross the boundary in each direction. computer architecture
Jul 21, 2023 Litmus Tests and Store Buffering How a five-line litmus test distinguishes total store order from sequential consistency, why the x86 store buffer permits a forbidden outcome, and what each outcome costs to rule out. systems programming
Jan 30, 2023 Cache Line Transfer, False Sharing, and the Cost of Contention Why an atomic operation on an uncontended location is cheap and on a contended one is not, what coherence protocol traffic each attempt generates, and how padding and sharding change the shape of the cost. systems programming
Dec 30, 2022 Spinlock Design from Test-and-Set to Ticket Locks How a test-and-set lock starves its waiters, why test-and-test-and-set helps, and how a ticket lock turns a race into a queue without a fairness guarantee. systems programming
Apr 22, 2022 Atomics and Contention in Counters and Aggregates Why a single global atomic counter serialises a kernel, how per-warp and per-block aggregation cuts that traffic, and which failure modes survive the optimisation. gpu computing