Tag
mmio
- Jun 12, 2026 Memory-Mapped Registers and the Ordering Rules Behind a Store How a device BAR becomes an address the core can load and store, why a posted write is not a completed write, and what a read-back actually guarantees. computer architecture
- Jun 4, 2025 Emulated MMIO: Instruction Decode, Register Semantics, and Exit Storms How a write to an emulated device register becomes a trap, what the hypervisor must decode before it can act, and why a driver that pokes registers in a loop degrades an entire host. virtualization
- Apr 12, 2025 Cacheability, Write-Combining, and Mapping Device Memory How page attributes control caching for MMIO and DMA, what happens when a load is speculatively reordered past a device write, and why the mapping must be uncached. memory systems
- Oct 10, 2024 The Interception Surface of a Virtual GPU A GPU presents a register file, a bus-mastering DMA engine, and an interrupt source at once; sharing one means deciding which of the three the host keeps control of. gpu computing
- Aug 28, 2023 Ordering Across the Device Boundary: DMA, MMIO, and Posted Writes Why a device can read stale data after a synchronising store, how posted writes hide completion, and which barriers cross the boundary in each direction. computer architecture