Tag
nand-flash
- Sep 16, 2026 Erase Blocks, Pages, and the Asymmetry That Shapes Flash Storage Why NAND programs a page once and erases a whole block, and how that mismatch forces every layer above the device to maintain a mapping and a collector. filesystems
- Sep 3, 2026 Error Correction in NAND: From Hard Bits to Soft Read Retry How BCH and LDPC codes absorb the raw bit error rate of a flash page, why soft-decision decoding needs several reads at shifted reference voltages, and what happens when correction runs out. hardware engineering
- Apr 27, 2026 How a NAND Cell Stores a Bit: Threshold Voltage and Read Levels The floating-gate transistor, the programmed charge that shifts its threshold, and why adding levels to a cell shrinks the margin every read decision depends on. hardware engineering
- Jan 14, 2026 Page Program and Block Erase: The Asymmetry That Shapes Flash Software Why a flash array writes in pages of a few kilobytes but can only be cleared in blocks of hundreds, what that costs in area and time, and how the asymmetry propagates upward. hardware engineering
- Nov 13, 2024 Channels, Dies, and Planes: How a Flash Controller Reaches Its Throughput A single flash die serves one operation at a time, so drive throughput comes from concurrency across channels and planes; the arithmetic of that concurrency sets the queue depth a workload needs. hardware engineering