Tag
page-tables
- Feb 9, 2026 Address Translation Across Host and Device A GPU access may traverse three translation stages, and where the stages live determines whether a shared address space is cheap, whether faults are recoverable, and what a migration can move. gpu computing
- Feb 1, 2026 Nested Paging: Two-Dimensional Translation for Virtual Machines How a guest physical address becomes a host physical address, why the walk cost multiplies, and which workloads suffer most from the second level of tables. memory systems
- Nov 30, 2025 Large Pages: What 2 MiB Granularity Buys and What It Breaks How huge pages collapse page-table levels and extend translation reach, why physical contiguity is the binding constraint, and where the memory waste becomes unacceptable. memory systems
- Nov 4, 2025 Walking a Multi-Level Page Table How four levels of tables turn a 36-bit page number into a frame, what each level costs in memory and cache misses, and why the walk is not free even when it succeeds. memory systems
- Sep 30, 2025 NX and the End of Injected Shellcode Marking the stack and heap non-executable removed the simplest payload, and the cost of that removal is paid on every page table entry and every legitimate JIT. security
- Aug 17, 2025 Splitting a Virtual Address into Page Number and Offset Why translation happens at page granularity, how the address bits divide between frame number and offset, and what that division costs in fragmentation and alignment. memory systems
- Jul 31, 2025 Reverse Mapping: Finding Every Page Table That Points at a Frame Why the kernel needs to go from a physical frame back to its mappings, how the reverse index is built and maintained, and what it costs in memory and lock contention. memory systems
- May 22, 2025 Dynamic Address Translation and the 16 MB Line How a two-level segment and page table turns a 24-bit virtual address into a real one, why the page tables themselves had to live in real storage, and what the 16 MB ceiling forced. computing history
- May 6, 2025 The TLB, Associativity, and What a Miss Actually Costs How the translation cache is organised, why it is small and fully associative, what the hardware does on a miss, and which access patterns destroy its hit rate. memory systems
- Apr 12, 2025 Cacheability, Write-Combining, and Mapping Device Memory How page attributes control caching for MMIO and DMA, what happens when a load is speculatively reordered past a device write, and why the mapping must be uncached. memory systems
- Mar 3, 2025 The Anatomy of a Context Switch Which registers are saved, where they go, why the switch costs more than the save, and how address-space tags avoid flushing the translation cache. operating systems
- Jan 3, 2025 Nested Paging: The Two-Dimensional Walk and the Cost of a Single Guest Access How EPT and NPT turn every guest memory access into two page walks, what an EPT violation reports, and why the hardware page-walk cache decides whether nested paging is cheap or ruinous. virtualization
- Jun 14, 2024 Page Tables for Sparse Virtual Textures How a texture is addressed through a page table, what happens when a page is missing during sampling, and how feedback selects the pages to load. computer graphics
- Feb 19, 2024 What fork Copies, and Why Copy-on-Write Defers Almost All of It How the kernel duplicates an address space by sharing page frames read-only, what a write does to break the sharing, and why fork without exec is expensive. operating systems
- Jan 20, 2024 Entering Long Mode From a Boot Loader The exact register sequence that turns on 64-bit addressing on x86-64, why paging must be enabled in the same instruction that commits to long mode, and the page tables that must exist beforehand. operating systems
- Dec 15, 2023 Shadow Page Tables: Keeping Two Guest Mappings Consistent With One Hardware Walk Why a hypervisor must build its own page tables from the guest's, which guest writes force a rebuild, and how the reverse-map and write-protection machinery bounds the cost of keeping them honest. virtualization
- Sep 19, 2023 Kernel Decompression and Physical Relocation Why a compressed kernel image relocates itself before decompressing, how the position-independent stub finds free memory, and what has to change in the page tables when the kernel moves. operating systems
- Aug 12, 2023 Page Table Mirroring Between CPU and Device How the kernel lets a device driver snapshot a process page table, why the snapshot needs an invalidation callback, and what breaks when the two disagree. gpu computing