Tag
pcie
- Sep 16, 2026 Posted Writes and the Ordering Rules a Device Must Respect Why PCIe memory writes are fire-and-forget, which transactions may pass which, and how a device orders its data ahead of its interrupt so the handler sees a completed transfer. hardware engineering
- Jun 12, 2026 Memory-Mapped Registers and the Ordering Rules Behind a Store How a device BAR becomes an address the core can load and store, why a posted write is not a completed write, and what a read-back actually guarantees. computer architecture
- Apr 19, 2026 Pinned Host Memory and Why Pageable Transfers Cannot Be Asynchronous Why a copy engine cannot be handed an ordinary host pointer, what the driver does instead, and how the staging buffer turns an asynchronous copy into a synchronous one. gpu computing
- Jan 27, 2026 PCIe Topology and Bus-Device-Function Enumeration How a host walks a tree of bridges and switches, how each function is named by bus, device, and function number, and why configuration space is a per-function address space. hardware engineering
- Dec 8, 2025 Link Training and the Width a PCIe Link Settles On What the link state machine exchanges before a single packet moves, how width and lane ordering are agreed, and why a link can train down to a fraction of its slot capability. hardware engineering
- Nov 21, 2025 PCIe Lanes and the Three Layers That Carry a Transaction How a PCIe transaction is assembled from transaction layer packets, sequence-numbered data link packets, and physical layer symbols across one or more lanes. hardware engineering
- Mar 15, 2025 Host-Mapped Memory over PCIe: Zero-Copy Access and Its Latency Wall What happens when a kernel dereferences host memory directly across the bus, why write-combining changes the cost, and the access patterns that make it worth doing. gpu computing