Tag
register-access
- Feb 4, 2026 Clock Gating, Peripheral Enable Order and the Write That Disappears Why a peripheral register write does nothing until its bus clock is enabled, why enabling order matters for parts with dependency chains, and how to diagnose the silent failure. embedded systems
- Jan 9, 2026 Masking Interrupts, Priorities, and Exclusive Access Without an OS The three mechanisms a bare-metal core offers for making a shared update atomic, what each one costs, and how to pick between them per invariant. embedded systems
- May 30, 2025 What volatile Guarantees in Memory-Mapped Register Access volatile forces a compiled access to happen, but it does not make the access atomic, ordered, or visible to the device in the order the source implies. embedded systems
- Jul 17, 2024 Read-Modify-Write Hazards in Peripheral Registers Why assigning through a bit-set idiom corrupts registers the hardware also writes, how write-one-to-clear flags interact with that idiom, and what surrogate registers buy. embedded systems
- Jan 10, 2023 Relocating the Vector Table and Running It from RAM How the table base register changes where exceptions dispatch, why a misaligned base fails silently, and what a writable copy of the table enables. embedded systems