Tag
synthesis
- Sep 8, 2026 Inferred Latches: Why an Incomplete Branch Becomes State How a combinational block that fails to assign its output on every path forces the synthesis tool to infer a level-sensitive latch, and which coding shapes create that condition. hardware engineering
- Aug 6, 2026 State Encoding: Why the Same State Machine Can Cost Three Flops or Eight How binary, one-hot, and Gray encodings trade register bits against next-state logic depth, and why the encoding chosen in code is not necessarily the encoding built. hardware engineering
- Jun 3, 2026 Equivalence Checking: Proving a Netlist Matches Its RTL How combinational equivalence is reduced to a miter of two circuits and a satisfiability question, why sequential transformations break that reduction, and where the proof stops being cheap. hardware engineering
- Oct 23, 2025 Metastability: What a Two-Flop Synchronizer Buys and What It Cannot Why a flip-flop that samples a changing asynchronous input can hover between logic levels, how the resolution failure rate falls exponentially with the time allowed, and why buses cannot be crossed one bit at a time. hardware engineering
- Oct 8, 2025 Block RAM Primitives and Memory Inference from RTL How dedicated memory blocks are structured internally, why inference from an array declaration produces different hardware than instantiation, and how read-during-write behaviour decides correctness. hardware engineering
- May 17, 2024 Register Retiming: Moving Flip-Flops Across Combinational Logic How a retiming tool redistributes registers along a path without changing the function, what the legal moves are, and why the resulting netlist no longer matches the RTL that was written. hardware engineering