Tag
timing-closure
- Oct 23, 2026 Setup and Hold Slack: Reading a Static Timing Report How arrival and required times are propagated through a timing graph, why setup and hold checks run in opposite directions, and how skew, derating, and path exceptions change the verdict. hardware engineering
- Feb 27, 2026 Placement, Routing, and Congestion in the Logic Array How the placer decides where each cell goes, how the router allocates wire segments, and why a design can fail to route while the array looks half empty. hardware engineering
- Oct 17, 2025 Retiming and Balancing the Stages of a Datapath How logic is moved across pipeline registers to shorten the longest stage, which moves are legal, and why a balanced pipeline is a fixed-point problem rather than a partition. computer architecture
- Jun 22, 2024 Retiming, Pipelining, and Register Balancing in the Fabric How moving registers across combinational logic changes which resources a path traverses, why the fabric makes retiming cheaper than in an ASIC, and where the technique stops helping. hardware engineering
- May 17, 2024 Register Retiming: Moving Flip-Flops Across Combinational Logic How a retiming tool redistributes registers along a path without changing the function, what the legal moves are, and why the resulting netlist no longer matches the RTL that was written. hardware engineering