Tag
topology
- Oct 4, 2026 Non-Transparent Bridges and Multi-Host PCIe Topologies Why two root complexes cannot simply be cabled together, how a non-transparent bridge presents a translated address window to each side, and what the doorbell handshake does not guarantee. hardware engineering
- Mar 24, 2026 Marching Cubes and the Ambiguity at a Cell Face How a 256-entry lookup table turns a scalar grid into triangles, why the case count is not 256, and how a saddle on a cell face can be triangulated two incompatible ways. computer graphics
- Feb 26, 2026 Replica Packing and Topology Constraints Tensor parallelism turns a model into a group of devices that must be co-located and upgraded together. That group, not the individual replica, is the unit a scheduler can place. inference systems
- Jan 27, 2026 PCIe Topology and Bus-Device-Function Enumeration How a host walks a tree of bridges and switches, how each function is named by bus, device, and function number, and why configuration space is a per-function address space. hardware engineering
- Dec 5, 2025 Marching Cubes and the Case Table That Cannot Be Interpolated How a 256-entry table turns a cube of eight samples into triangles, why edge interpolation places the vertices, and where the classic ambiguity creates holes or spurious connections. scientific computing
- Jul 29, 2024 Composing a Parallelism Layout From a Memory and Bandwidth Budget Data, tensor, pipeline, and shard dimensions interact non-linearly. A procedure for choosing their sizes from per-device memory, interconnect tiers, and batch constraints. deep learning
- Jun 14, 2023 Peer-to-Peer Transfers and the Topology That Decides Whether They Work What peer access actually establishes in the device page tables, why the path between two devices is not the path through the host, and how to read the topology. gpu computing