Tag
vector-isa
- Apr 1, 2026 Mask Registers, Tail Handling, and the Cost of the Last Iteration How per-lane execution masks replace the scalar remainder loop, what inactive lanes still consume, and why vector length control and tail policy decide whether the last iteration is cheap. computer architecture
- Oct 26, 2025 Fixed-Width SIMD Lanes Versus Scalable Vector Registers Why one design bakes the vector length into the instruction encoding and the other reports it at run time, and how each choice propagates into code generation, binary compatibility, and register pressure. computer architecture
- Sep 3, 2025 Strided, Indexed, and Gather Memory Access Why contiguous vector loads map onto ordinary cache lines while strided and indexed accesses turn into many element transactions, and where the memory system stops being able to keep a vector unit fed. computer architecture