Tag
write-combining
- Apr 28, 2026 Store Buffers and the Total Store Order That Replaces Sequential Consistency How a per-core store buffer hides cache-miss latency, exactly which four orderings TSO keeps, and why load-load reordering is forbidden while load-store is not. computer architecture
- Mar 15, 2025 Host-Mapped Memory over PCIe: Zero-Copy Access and Its Latency Wall What happens when a kernel dereferences host memory directly across the bus, why write-combining changes the cost, and the access patterns that make it worth doing. gpu computing