Tag
x86
- Jun 28, 2024 Store Buffers and the x86-TSO Model How a per-core write buffer leaves store-load as the only program-order pair that may invert, why forbidding it would defeat the buffer, and what a locked instruction orders. memory systems
- Jan 7, 2024 The Reset Vector and the First Instruction Executed Why an x86 processor begins executing at 0xFFFFFFF0 in real mode, how that address reaches the firmware ROM, and what the sixteen bytes at the top of memory must contain. operating systems