Compilers · Cluster
Intermediate Representation
SSA, control-flow graphs, and IR design.
- 01 Three-Address Code as the Contract Between Front End and Back End Why compilers flatten expression trees into single-operator instructions with named temporaries, what optimization gains from that shape, and which machine constructs the form cannot express directly.
- 02 Building Basic Blocks and Control-Flow Graphs from Linear Code How leaders split a linear instruction stream into basic blocks, how edges are derived from branches, and which irregularities in real control flow break the simple model.
- 03 Minimal SSA Construction from Dominance Frontiers How the Cytron placement algorithm decides where phi functions belong using dominance frontiers, and why placing them minimally changes what later passes can assume.
- 04 Phi Functions: Parallel Semantics and the Out-of-SSA Problem Why phi inputs are read simultaneously rather than in sequence, how that forces the lost-copy and swap problems on elimination, and how edge splitting and register coalescing resolve them.
- 05 Sparse Conditional Constant Propagation Across the SSA Graph How SCCP combines constant propagation with reachability so that unreachable branches stop contributing values, and why the sparse formulation converges faster than a dense lattice iteration.
- 06 Memory SSA: Giving Loads and Stores Def-Use Chains How aliasing prevents ordinary SSA from naming memory locations, what the memory-phi construction buys for store-to-load forwarding, and why the result must be abandoned rather than verified.
- 07 Instruction Scheduling and Its Dependence on the Graph How list scheduling trades register pressure against parallelism, what latency and resource tables must contain, and why the scheduler sees a different graph from the one the optimiser built.
- 08 Building the Interference Graph from SSA Live Ranges Why SSA live ranges interfere only at phi-connected join points, how that makes the graph chordal, and what the colouring and spilling decisions cost once the graph is built.
- 09 Sea of Nodes: Scheduling Without a Fixed Instruction Order How a graph-based IR represents data, control, and memory dependences as edges with no block order, what scheduling then becomes, and which analyses become harder when nothing is sequential.
- 10 Poison, Undef, and What an IR Must Say About Speculation How deferred undefined behaviour lets an IR move and duplicate operations that might trap, why poison propagates through flags like nsw, and what a freeze instruction buys in exchange for lost optimisation.