GPU Computing · Cluster
Compute APIs
Vendor and portable acceleration interfaces.
- 01 The Contract a Compute API Encodes Kernels, launch geometry, memory objects, and queues: the four obligations every GPU acceleration interface must satisfy, and why each one is spelled differently across vendors.
- 02 Launch Geometry and the Arithmetic of Thread Indexing How a grid extent becomes a linear identifier, what the block and grid dimension limits are, and why a non-multiple block size leaves a guard predicate in every kernel.
- 03 OpenCL Objects, Contexts, and Runtime Compilation The platform-to-queue object graph in OpenCL, what a program build actually produces, and how vendor portability breaks at kernel compile time rather than at run time.
- 04 Command Queues, Events, and Cross-Stream Ordering What an in-order queue actually guarantees, how events turn streams into a dependency graph, and why the same code is correct under CUDA streams and wrong under Vulkan barriers.
- 05 Host-Device Transfers and the Cost of Crossing the Bus Pinned versus pageable host memory, why a blocking copy costs more than its bandwidth suggests, and where the staging copy inside the runtime comes from.
- 06 PTX, SASS, and What a Fat Binary Contains The two-stage compilation path from CUDA C to machine code, why PTX survives an architecture change and SASS does not, and how the loader picks a cubin from an embedded archive.
- 07 Portable Single-Source Layers and Where They Leak How SYCL, OpenMP offload, and Kokkos present one source file for host and device, and which abstractions fail to compile, fail to perform, or silently diverge in results.
- 08 Capability Negotiation Across Architectures Choosing a backend and a kernel variant at load time: what to query, how to key a selection cache, and where feature detection diverges from the specification.
- 09 Driver-Level Runtime Compilation and Module Loading The chain from kernel source to a loadable module: intermediate collection, per-device lowering, cached artefacts, and the failure modes at each stage of the load.
- 10 Atomics, Fences, and Memory Scopes in Device Code What a device-scope atomic orders, why relaxed operations reorder across a barrier, and how scope qualifiers change what a fence must flush.