GPU Computing · Cluster
GPU Memory
Coalescing, shared memory, and hierarchies.
- 01 The Address Spaces a GPU Kernel Can Touch How global, local, shared, and constant memory differ in scope, lifetime, and backing store, and why the compiler must know which space a pointer refers to.
- 02 How a Warp Turns Thirty-Two Loads into Memory Transactions The request the memory system actually receives from a warp-wide load, why the unit of transfer is a 32-byte sector rather than a cache line, and how a partial write forces a read first.
- 03 Stride, Misalignment, and the Cost of a Bad Layout How stride and alignment interact to add sectors to every warp request, why a row-major array accessed by column collapses bandwidth, and what a shared-memory transpose costs in return.
- 04 Bank Conflicts Inside GPU Shared Memory How a shared-memory address selects one of thirty-two banks, when the hardware serves a warp in a single pass, and why padding a tile by one column removes a thirty-two-way serialization.
- 05 Tiling Through Shared Memory and Overlapping the Load The reuse arithmetic that decides a tile size, why a register tile on top of a shared tile cuts scratchpad traffic again, and how an asynchronous copy lets the next tile load while the current one is computed.
- 06 Register Pressure and the Spill into Local Memory Why the register file caps how many threads an SM can host, how the compiler trades registers for scattered memory traffic when it runs short, and why the spilled addresses still coalesce.
- 07 Constant Memory and the Read-Only Load Path How a 64 KB host-written bank gets a fast path to the pipelines, why uniform reads inside a warp are almost free while divergent ones serialize, and what the non-coherent load promises the compiler.
- 08 L2 Slices, Address Hashing, and Partition Camping Why the last-level GPU cache is physically distributed across memory controllers, how addresses are spread over it, and how a stride that resonates with the mapping leaves most of the memory system idle.
- 09 Row-Buffer Locality Inside GPU DRAM How DRAM banks, open-row policies, and bank groups shape what a memory controller can schedule, and why many concurrent streams lower achieved bandwidth without moving more bytes.
- 10 Atomic Contention and the L2 as a Serialization Point Why a global atomic executes at the cache slice that owns its address, how a hot counter turns a parallel machine into a queue, and which reductions avoid the queue entirely.