Memory Systems · Cluster
Cache Hierarchy
Locality, coherence, and replacement.
- 01 The Memory Gap and the Arithmetic of Average Access Time How the latency of each level combines into one average, why a small miss rate can dominate the total time, and where the model stops describing real hardware.
- 02 Set Associativity and the Address Bits a Cache Decodes How a physical address splits into tag, index, and offset, why direct-mapped and fully associative arrays are the two ends of one trade, and what conflict misses actually cost.
- 03 Write-Back, Write-Through, and the Cost of a Dirty Line How a cache decides whether a store waits for memory, what write-allocate does to a partial line, and why the dirty bit turns an eviction into a second transaction.
- 04 Replacement Without Exact LRU: Reference Bits and Clock Hands Why a cache cannot maintain a true LRU stack at speed, how one reference bit per line and a rotating hand approximate it, and where the approximation picks the wrong victim.
- 05 Stride Prefetchers and the Timing Problem of Prefetch Distance How a stream prefetcher detects a recurring address delta, why prefetching too early evicts useful lines, and how accuracy, coverage, and timeliness trade against each other.
- 06 MESI Transitions and the Traffic an Invalidation Generates What each coherence state permits, which transactions move a line between them, and why a false sharing pattern produces more bus traffic than the data it writes.
- 07 Inclusive, Exclusive, and Non-Inclusive Last-Level Caches What the inclusion property buys the coherence protocol, why a back-invalidation hurts an inclusive L2, and how a non-inclusive design changes where the snoop filter lives.
- 08 Virtually Indexed Caches and the Page Coloring Problem Why a cache can start its lookup from a virtual address and finish with a physical tag, when that creates synonyms, and how page coloring controls which sets a process occupies.
- 09 Miss Status Holding Registers and Memory-Level Parallelism How a cache tracks outstanding misses by line rather than by request, why secondary misses merge, and how the number of MSHRs caps the parallelism a core can expose.
- 10 Re-Reference Interval Prediction in Shared Last-Level Caches How a two-bit prediction value per line resists scan thrashing, why set dueling picks a policy without simulating every access, and where shared-cache insertion policy goes wrong.