Memory Systems · Cluster
Virtual Memory
Paging, address translation, and page tables.
- 01 Splitting a Virtual Address into Page Number and Offset Why translation happens at page granularity, how the address bits divide between frame number and offset, and what that division costs in fragmentation and alignment.
- 02 Walking a Multi-Level Page Table How four levels of tables turn a 36-bit page number into a frame, what each level costs in memory and cache misses, and why the walk is not free even when it succeeds.
- 03 The TLB, Associativity, and What a Miss Actually Costs How the translation cache is organised, why it is small and fully associative, what the hardware does on a miss, and which access patterns destroy its hit rate.
- 04 Demand Paging and the First-Touch Fault What happens between mmap returning and a page becoming resident, the three fault outcomes a handler must distinguish, and why anonymous memory is zeroed lazily.
- 05 Clock, Second Chance, and the Cost of Approximating LRU How a reference bit turns a circular scan into a cheap replacement policy, what the scan rate reveals about memory pressure, and where the approximation breaks down.
- 06 Large Pages: What 2 MiB Granularity Buys and What It Breaks How huge pages collapse page-table levels and extend translation reach, why physical contiguity is the binding constraint, and where the memory waste becomes unacceptable.
- 07 Reverse Mapping: Finding Every Page Table That Points at a Frame Why the kernel needs to go from a physical frame back to its mappings, how the reverse index is built and maintained, and what it costs in memory and lock contention.
- 08 Kernel Page Table Isolation and What It Costs on Every Trap Why splitting the kernel into a separate address space defends against speculative reads, how the switch is arranged to be nearly free, and where the remaining cost lands.
- 09 Nested Paging: Two-Dimensional Translation for Virtual Machines How a guest physical address becomes a host physical address, why the walk cost multiplies, and which workloads suffer most from the second level of tables.
- 10 Cacheability, Write-Combining, and Mapping Device Memory How page attributes control caching for MMIO and DMA, what happens when a load is speculatively reordered past a device write, and why the mapping must be uncached.