Multiplexed Address and Data Buses in a Forty-Pin Package

A forty-pin dual in-line package has forty pins and no more. Subtract the two supply pins, the ground pins, the clock input, and the handful of control and status outputs a processor needs to describe what it is doing, and the remainder is what is left for the bus. A sixteen-bit address bus plus an eight-bit data bus is twenty-four pins, which fits, but only if almost nothing else is required. Processors that needed more address lines than that had to find another arrangement, and the one they found changes the timing of every memory access in the machine.

The 8080 and the 6502 kept the buses separate

The Intel 8080 uses all forty pins and does not multiplex its buses. Sixteen address outputs, eight data pins, and a set of control and status lines occupy the package, and the price is paid in supply rails: the part requires +5 V, -5 V, and +12 V, because the process of the period could not build fast enough logic at a single low voltage. A memory device connects to the address lines directly and sees the address for the entire machine cycle, with no external component in the path.

The MOS 6502 takes the same position with a different budget. Sixteen address lines, eight data lines, and a clock that is divided internally into two phases, so that the data bus is driven during one phase and released during the other. No latch is needed for memory, and a designer wires the address lines straight to the RAM and the ROM. The cost is that the bus is only half-occupied: during the phase when the processor is not driving data, the bus is available to nobody in the simple case, and a machine that wants to use it must arrange its own arbitration.

Both of these parts are honest about their bus. A designer reading the timing diagram sees the address lines asserted, then the read or write strobe, then the data, and every interval is a property of the processor. The only external timing component is the memory’s own access time.

Three answers to the same pin budget

The Intel 8085 fits a sixteen-bit address into a forty-pin package by sharing eight of the address lines with the data bus. Pins AD0 through AD7 carry the low half of the address at the start of a machine cycle and carry data for the rest of it. Pins A8 through A15 are dedicated address outputs and hold their values for the whole cycle. A separate output, ALE, goes active at the start of the cycle to announce that the low address byte is on those shared pins.

ALE is the entire interface between the processor and the latch. Its falling edge is the moment the low address byte is guaranteed to be valid and is about to disappear, so an external eight-bit latch clocked on that edge captures it and holds it for the remainder of the cycle. With the latch in place, the memory sees a stable sixteen-bit address for the whole cycle, exactly as it would with a non-multiplexed part. The difference is that the address arrives at the memory through the latch, and the latch’s propagation delay is subtracted from the memory’s access window.

The 8086 extends the same idea to a wider machine. It has twenty address lines and a sixteen-bit data bus, and it multiplexes AD0 through AD15, so the low sixteen address bits share pins with data. The top four address bits share pins with status outputs, and the bus high enable signal shares with a further status line. A system built around it needs two latches for the address and, because sixteen data lines cannot drive a large bus directly, a set of bidirectional transceivers. The pin count saved is substantial, and the component count added is three or four packages.

The latch is not optional: any access that needs the full address must have
captured AD0..AD7 before the processor replaces them with data. On the 8085,
ALE marks that instant. A memory write, state by state:

  state       T1              T2              T3
  A8..A15     ---------------- stable ------------------
  AD0..AD7    low addr        ------------- data out ----
  ALE         active, falls at the end of T1
  WR                                          active

Nothing in the processor repeats the low address. After T1 the latch is the
only copy of it, and every device on the bus must decode from the latch.

The Z80 takes the third route. It keeps the full sixteen-bit address bus and the separate eight-bit data bus, so no latch is required, and it uses the half of the opcode fetch cycle in which the bus would otherwise be idle to place a seven-bit row address on A0 through A6 and assert a refresh output. Dynamic memory, which must have its rows read periodically to retain data, gets that refresh from the processor with no separate controller and no stolen cycles. The processor is paying for the wider bus with a more complex internal sequencer rather than with external parts. A machine that shares its memory between the processor and a display adds a second claimant to the same bus, which is the situation described in cycle counting under video contention.

What the latch does to the access window

The arithmetic is the same for every multiplexed design. A machine cycle is a fixed number of clock periods. The address is valid at the end of the first one, the latch holds it a short time later, and the memory has from that point until the processor samples the data. Whatever the latch costs comes directly out of the memory’s budget.

Consider an 8085 running from a 6.144 MHz crystal, which the part divides by two to produce a 3.072 MHz clock. One clock period is about 325 nanoseconds, and a memory read or write machine cycle occupies three of them, so the cycle is a little under a microsecond. A bipolar latch adds a propagation delay in the tens of nanoseconds, and the processor requires its data inputs to be stable for a setup interval before the sampling edge. The memory is left with most of the cycle but not all of it.

/* Access window for a three-state machine cycle, from published timing.
   All durations in nanoseconds; the result is arithmetic, not a measurement. */
#define T_STATE       325.0   /* one clock period at 3.072 MHz */
#define CYCLE_STATES  3.0

double window(double latch_delay, double data_setup)
{
    double cycle = T_STATE * CYCLE_STATES;   /* about 975 ns */
    return cycle - latch_delay - data_setup;
}

/* A 25 ns latch and a 100 ns setup leave roughly 850 ns of memory time. */

The consequence is structural rather than incidental. Buying faster memory does not recover the latch delay, because the memory does not see the address until the latch has settled. The remedies are a faster latch, a shorter cycle, or a processor that does not multiplex, and only the last of those removes the component.

Wait states work in the other direction. Holding the READY input low inserts whole clock periods into the cycle, and each inserted period extends the time available to the memory by one clock period. That is the correct tool for slow memory or for a peripheral that cannot respond within the nominal window, and its cost is paid on every access to that device. A machine with a slow ROM and fast RAM inserts states only for the ROM, which is why the wait-state logic is usually qualified by the chip select of the device that needs it.

Failures that come from the shared pins

The first failure is a strobe that arrives at the wrong time. If the latch opens while the low address byte is still changing, the memory receives a transient address and the read returns data from a location the program did not name. The ALE pulse is specified relative to the address lines for exactly this reason, and a designer who derives a latch clock from some other signal, such as a delayed copy of the read strobe, gets a latch that closes at an unpredictable point.

The second is bus ownership. When a DMA controller takes the bus, the processor floats its pins and asserts a hold acknowledge. The latch, however, still holds the last address the processor placed there and continues to drive its outputs. A DMA transfer that drives the address bus while the latch drives the same lines puts two drivers on one net. The latch’s output enable must be tied to the same arbitration that floats the processor.

The third is the assumption that the address is available for the whole cycle. A peripheral that decodes its chip select from the shared pins alone sees those pins change to data halfway through the cycle and deselects itself mid-transfer. Peripherals must decode from the latched address, or from the high lines combined with a qualified strobe. The distinction matters most for devices that hold the bus for longer than a cycle, such as a controller that performs a multi-byte transfer after a single command.

The fourth is subtler. A wait state lengthens the cycle but does not move the moment the address becomes valid, so a device that starts an operation on the write strobe and finishes it on a fixed internal timer sees the cycle stretch underneath it. Devices with their own timing need their own handshake rather than an inference from the bus. The same reasoning explains why memory-mapped and port-mapped devices need different decoding logic even on the same processor: the address space a device occupies is defined by which control signals the processor asserts, not by the width of the bus.

None of these problems is exotic. They are the ordinary consequence of a package with too few pins, and every machine built on a multiplexed bus solved them somewhere between the processor and the first memory chip. What the multiplexing buys is a wider address in a smaller package; what it costs is a latch in the address path and a set of rules that every device on the bus must follow.