Tag
bus-timing
- Sep 22, 2025 Multiplexed Address and Data Buses in a Forty-Pin Package Multiplexed address and data pins let a processor with more address lines than pins reach memory, at the cost of an external latch and a shortened access window. computing history
- Sep 15, 2025 Shared-Bus Arbitration and the Clock Ceiling That Ended It How a multiplexed parallel bus runs one transaction at a time, how a central arbiter decides which master owns the wires, and which electrical limits forced the move to point-to-point links. hardware engineering
- Sep 6, 2025 Two Address Spaces: Port-Mapped and Memory-Mapped I/O Decoding Why the 8080 family reserved a separate 256-byte I/O space, how the control signals distinguish it from memory, and what each arrangement costs in address decoding and instruction width. computing history