What a Sleep Mode Actually Turns Off

Vendors name their low-power states inconsistently: sleep, deep sleep, stop, standby, hibernate, shutdown. The names carry no portable meaning, and two parts with the same label can differ by orders of magnitude in current. What is portable is the set of physical actions a state can take, because there are only a handful of them, and every named state is a particular combination.

The five things a state can do

Every low-power mode on a CMOS microcontroller is built from some subset of these:

1. Gate the clock to a block, so its flip-flops stop toggling and only leakage remains.
2. Stop the system clock source entirely, which stops the core and most peripherals but leaves the regulator and the always-on domain running.
3. Switch or disable the regulator, replacing the main linear or buck supply with a low-current reference, or removing the core rail altogether.
4. Remove power from a domain, which eliminates leakage in that domain but also loses everything stored in it.
5. Bias the substrate or reduce the supply voltage below the level needed for normal operation, cutting leakage at the cost of losing state and paying a longer recovery.

A state named “stop” usually performs the first three; a state named “standby” usually performs the fourth on the core domain and keeps a small always-on domain with a wake-up controller, a real-time counter, and some retention RAM.

The distinction that matters for an energy budget is which of these a state performs, not what it is called. A state that only gates the clock still draws leakage from every powered transistor, which on a modern process is a substantial fraction of the active current at low frequency. A state that removes the core rail draws leakage from nothing in that domain but pays a startup cost when it returns.

Where the current goes when the core is stopped

Leakage is the floor. In a CMOS gate, subthreshold conduction through the off transistors continues regardless of clocking, and it scales with the total width of the powered transistors, with temperature, and exponentially with threshold voltage. The supply enters through drain-induced barrier lowering: a lower drain voltage raises the effective threshold and so cuts the subthreshold current, by an amount that depends on the process. That is why a state that lowers the core rail beats one that only stops the clock: once the clock is stopped, leakage is essentially the whole remaining current, and only a voltage change reduces it.

Around the core sit the parts that never stop: a bandgap reference, a low-power oscillator, brown-out detection, a wake-up timer, and the always-on logic that watches for an interrupt. Each has a datasheet figure in the microamp range, and they add rather than overlap. A part whose headline sleep current is 1 µA is usually quoting a configuration with the brown-out detector off, the watchdog off, and the internal low-power oscillator as the only running clock. Enabling the brown-out detector and the watchdog adds their currents to the figure, which is why the headline number and the achievable one differ.

The gap between the headline figure and a real configuration is a common reason a design misses its budget. The datasheet conditions are printed, usually in a footnote or a table column, and reading them is the first step of any sleep-mode decision.

Retention: the difference between waking and restarting

Removing power from a domain loses the registers, the SRAM contents, and the peripheral configuration. A part can offer a retention mode that keeps a subset of SRAM powered from a separate, very low-current rail while the core domain is off. The retained region is small, typically a few kilobytes, and it holds the variables that let the firmware restore its state instead of rebuilding it from flash.

Retention costs area and current. Each retained bit needs a biased, powered cell, so retention current scales with the size of the retained region, and the region is deliberately kept small for that reason. Firmware that needs to keep a large buffer across sleep has to either move it to external non-volatile memory or accept a higher sleep current.

The alternative to retention is reinitialisation: on wake, run the reset path, reconfigure every peripheral, and rebuild the state from whatever was saved in flash. That costs energy per wake, which becomes significant when wakes are frequent. The trade is a fixed sleep-current penalty against a per-wake energy penalty, and the crossover depends on the wake rate, which is why the cost of waking up and retention have to be evaluated together.

Reading the numbers correctly

Datasheet current figures are usually given at a stated temperature and supply voltage, and both move the answer. Leakage doubles roughly every 8 to 12 °C on typical processes, so a part specified at 25 °C can draw several times that current at 85 °C. A design whose budget assumes room temperature and whose enclosure reaches 60 °C has a budget that is wrong by a large factor.

Supply voltage matters just as much. The same state at 3.3 V and at 1.8 V is not the same state; leakage scales strongly with voltage, and some regulators have better quiescent current at one input voltage than another.

Then there is the measurement itself. A current in the microamp range is hard to measure with a shunt and a multimeter, because the meter’s own burden voltage changes the circuit’s behaviour and because the current is not constant. The usual method is to accumulate charge on a capacitor and measure the voltage change over a known interval, or to use a source-measure unit that holds the voltage constant. Either way the number obtained includes the board’s leakage, the decoupling capacitors’ leakage, and the measurement path, so the firmware’s contribution is a subtraction.

/* Entering the deepest state the part offers, with a wake on the
   real-time counter compare. The sequence is the part's own: the
   order matters because the regulator must be switched after the
   last peripheral that needs it is stopped. */
static void enter_deep_sleep(uint32_t wake_tick)
{
    rtc_set_compare(wake_tick);        /* arm the wake source first   */
    uart_disable();                    /* pins float otherwise       */
    gpio_set_all_analog();             /* no input buffers, no leakage */
    pm_select_low_power_regulator();
    pm_mask_unused_wake_sources();     /* a pending flag wakes anyway */
    __dsb();
    pm_enter_stop();                   /* returns on the wake event  */
    pm_select_main_regulator();
    clock_restore();
}

The order in the sequence is not stylistic. Arming the wake source before entering the state avoids a window in which the part sleeps with no reason to wake. Setting unused pins to analog removes the input buffers’ crowbar current, which on a floating digital input can be tens of microamps. Masking unused wake sources prevents a stale flag from turning a one-second sleep into an immediate return.

Why the deepest state is often the wrong choice

Each step deeper costs wake-up time. A clock-gated state resumes in a handful of cycles. A stop state with a switched regulator needs the regulator to settle and the oscillator to restart, which can take tens of microseconds. A standby state that removed power from the core needs a full boot sequence, which can take milliseconds.

When the device wakes once per second to sample a sensor, the time spent in the transition is not the issue; when it wakes every millisecond, the transition dominates and the deepest state is worse than a shallower one. The break-even is straightforward: the deep state wins when

$$I_{\text{deep}} , t_{\text{sleep}} + Q_{\text{wake}} < I_{\text{shallow}} , (t_{\text{sleep}} + t_{\text{wake}})$$

with $Q_{\text{wake}}$ the charge drawn during the transition, obtained by integrating the current over the wake profile at the operating voltage. Because $Q_{\text{wake}}$ is fixed per wake and the shallow state’s advantage grows with sleep duration, there is a wake interval below which the shallow state always wins. Computing that interval is a design step, not a tuning exercise.

A second reason the deepest state is often wrong is that it breaks things. Some peripherals lose their configuration, some pins change state during the transition, and a wake that arrives during the regulator ramp can be missed or can produce a partial reset. Debug access is often unavailable in the deepest states, which makes the behaviour of a failing unit unobservable. Choosing a state one step shallower than the deepest is a common engineering decision, and it is usually made because the failure modes of the deepest state are hard to diagnose rather than because the current saving is small.

What the modes do not control

No sleep mode reduces the current drawn by anything outside the microcontroller. A sensor in its own standby mode, an external memory device holding its chip select low, a regulator with poor light-load efficiency, and a pull-up on a line driven low all continue to draw. The microcontroller’s sleep current is one term in the board’s sleep current, and on many designs it is not the largest one.

The practical consequence is that sleep-mode selection has to be done against a measured board current, not against the part’s datasheet. Halting the firmware in its deepest state and measuring the assembled board gives the floor; the difference between that floor and the datasheet figure is the sum of everything the mode does not control. Reducing that difference is usually worth more than moving from one sleep state to the next, and the parts of it that the firmware can reach are covered in peripheral clock gating and autonomous transfer.