Embedded Systems

Cores, peripherals, and memory maps.

1. How a Microcontroller Memory Map Assigns Meaning to Every Address
2. Flash Wait States and the Cost of Fetching Instructions from Embedded Flash
3. Nested Interrupt Entry, Tail-Chaining and Late Arrival in the NVIC
4. Clock Gating, Peripheral Enable Order and the Write That Disappears
5. Bus Matrix Arbitration and What DMA Contention Costs the Core
6. GPIO Configuration Registers and the Reset States That Drive Pins

Startup code, vectors, and register access.

1. Where the Reset Vector and Initial Stack Pointer Come From
2. Getting Initialised Data and BSS Ready Before main Runs
3. What volatile Guarantees in Memory-Mapped Register Access
4. Read-Modify-Write Hazards in Peripheral Registers
5. What the Hardware Does Between an Interrupt and Its Handler
6. Relocating the Vector Table and Running It from RAM

Tasks, priority inversion, and deadlines.

1. How a Preemptive RTOS Scheduler Picks the Next Task
2. Blocking Primitives: How a Task Waits Without Spinning
3. Priority Inversion and How Bounded It Can Be
4. Rate-Monotonic Priority Assignment and Its Utilisation Bound
5. Response-Time Analysis for Fixed-Priority Task Sets
6. Deferred Interrupt Work: Splitting Handlers from Processing

I2C, SPI, CAN, and their failure modes.

1. Open-Drain Signalling and Arbitration on a Shared Two-Wire Bus
2. The Shift Register Behind SPI and Why There Are Four Clock Modes
3. UART Framing, Baud Rate Error, and the Overrun That Loses Data
4. CAN Frame Layout and Why Bit Stuffing Is Mandatory
5. Clock Stretching and Recovering a Bus Held Low by a Stuck Slave
6. Differential Signalling, Common-Mode Rejection, and Where to Put the Terminator

Sleep states, duty cycling, and energy budgets.

1. From Duty Cycle to Average Current and Battery Life
2. What a Sleep Mode Actually Turns Off
3. Wake-Up Latency and Its Energy Cost
4. Tickless Idle and Timer Reprogramming
5. Peripheral Clock Gating and Autonomous Transfer
6. Voltage and Frequency Scaling with a Performance Constraint

Bootloaders, A/B images, and rollback.

1. What a Bootloader Must Establish Before Jumping to an Application
2. Image Headers and Integrity Validation Before Execution
3. Dual-Bank Slots and How a Bootloader Picks One
4. Erase Granularity, Write Ordering, and Power Loss During a Flash Write
5. Chunked Transfer and Retransmission in Firmware Delivery
6. Trial Boot, Confirmation, and Automatic Rollback

Redundancy, watchdogs, and certification practice.

1. Deriving a Safety Integrity Level from Risk Parameters
2. Windowed Watchdogs and the Program-Flow Contract
3. Safe States and Fail-Silent Behaviour in Control Systems
4. Lockstep Cores and Comparator Logic in Safety Microcontrollers
5. Runtime Self-Tests and Diagnostic Coverage Measurement
6. Common-Cause Failure and What Design Diversity Actually Buys

Cross toolchains, debug probes, and tracing.

1. Anatomy of a Cross Toolchain: Triples, Sysroots, and Multilibs
2. Linker Scripts: Why Sections Have Two Addresses
3. Reading an ELF Image: Sections, Symbols, and DWARF
4. Intel HEX, Motorola SREC, and What a Programmer Actually Consumes
5. How a Probe Reads Memory Without the CPU: Debug Ports and Access Ports
6. Hardware Breakpoints, Watchpoints, and the Comparators Behind Them