Voltage and Frequency Scaling with a Performance Constraint

Dynamic power scales with the square of the supply voltage and linearly with frequency. That exponent is the reason voltage scaling is the most effective single knob in a power budget, and the reason it is also the most constrained: below some voltage the circuit does not meet timing, and the margin between “meets timing at this temperature” and “fails intermittently” is narrow.

The two knobs and their coupling

Frequency can be changed alone. On most microcontrollers the core clock is derived from a phase-locked loop or a prescaler, and halving the clock halves the dynamic power of the core. That is a linear saving, and it is available without any risk to correctness as long as the peripherals that depend on the clock are re-scaled with it.

Voltage cannot usually be changed alone in the other direction. A digital circuit’s maximum frequency is set by the longest path’s delay, and that delay grows as the supply falls. Reducing voltage without reducing frequency produces timing violations. Reducing frequency without reducing voltage leaves the voltage term untouched, so the quadratic gain is not realised.

The two therefore move together, and the operating point is a pair. The useful relation is that the maximum frequency at a given voltage is roughly proportional to $(V - V_{th})^2 / V$ in the long-channel alpha-power model, and in practice it is characterised empirically per part. A vendor’s operating-point table lists voltage and frequency pairs, and the pairs are not arbitrary: they are the points at which the part meets timing over the full temperature range with the stated margin.

The energy per operation at an operating point is the power divided by the frequency:

$$E_{\text{op}} \propto C V^2 + \frac{P_{\text{static}}}{f}$$

The first term falls with voltage squared. The second term rises as frequency falls, because the static power is paid for a longer time per operation. There is therefore a voltage below which further reduction increases the energy per operation rather than decreasing it. That minimum is the reason voltage scaling has a floor that is not set by timing.

/* Operating points, highest performance first. The table is the
   part's own: the voltages are not derivable from the frequencies. */
static const struct opp {
    uint32_t hz;
    uint16_t mv;
} opps[] = {
    { 48000000, 1800 },
    { 24000000, 1500 },
    {  8000000, 1200 },
    {   1000000, 1000 },
};

/* Pick the lowest point that meets the deadline for the work at hand. */
static const struct opp *select_opp(uint32_t cycles, uint32_t deadline_us)
{
    for (int i = sizeof opps / sizeof opps[0] - 1; i >= 0; i--) {
        uint32_t need_us = (uint64_t)cycles * 1000000u / opps[i].hz;
        if (need_us <= deadline_us)
            return &opps[i];          /* slowest point that still fits */
    }
    return &opps[0];
}

The selection rule is “slowest point that still meets the deadline”, not “fastest point available”. Running faster than necessary spends voltage-squared for time that was not the constraint.

The ordering of the transition

Changing an operating point is a sequence, and the order depends on the direction.

Going down in frequency, the frequency must be reduced before the voltage, because the circuit must remain within timing at the current voltage while the clock slows. Going up, the voltage must rise before the frequency, for the same reason in reverse. Reversing either order produces a window in which the part runs faster than the current voltage supports, and the resulting failure is a corrupted instruction stream rather than a clean fault.

The transition also takes time. A switched regulator’s output moves at a rate set by its inductor and its control loop, and a step from 1.0 V to 1.8 V can take tens of microseconds. During that time the core is either stalled or running at the old frequency, and the transition’s energy is part of the cost of using the operating point at all. A workload that would run for 50 µs at the higher point cannot amortise a 30 µs transition, so the scaling decision has to be made at a coarser granularity than the scheduler’s timeslice.

Some parts implement the sequencing in hardware, with a single register write that handles the ramp and the clock change in the correct order and stalls the core until both settle. That removes the ordering hazard from firmware and replaces it with a documented transition latency, which is the number the scheduler should use.

Choosing the operating point from the workload

The energy-optimal policy for a task with a known cycle count and a deadline is to run at the lowest operating point that finishes within the deadline. That is the classic result, and it holds when the transition cost is zero and when the power model is the simple one above.

Two corrections make it usable. The first is the transition cost: if moving between points costs more energy than the difference in execution, staying at one point is better. The second is that the deadline is often not the binding constraint; the constraint is the response time of a chain of tasks, and lowering one task’s operating point can move the whole chain’s completion later without violating its own deadline. The scheduling analysis that determines the chain’s timing is the same one that determines whether the operating point is feasible, and the two cannot be decided independently.

A practical policy therefore works in steps rather than continuously. The system declares a small number of operating points, the scheduler selects among them at task boundaries, and the selection uses measured execution times at each point rather than the nominal frequencies. Nominal frequency and achieved throughput differ by memory wait states, flash access time, and bus arbitration, and the ratio between them is not constant across the points. A part whose flash cannot deliver an instruction per cycle at the top frequency may gain much less than a factor of two from doubling the clock.

The temperature and process spread

The voltage at which a part meets timing is not a single number. It varies with process corner, and it varies with temperature in a direction that surprises people: at lower temperature, transistors are faster, so a part that meets timing at 85 °C usually also meets it at 25 °C. The exception is at very low temperature, where some effects reverse, and the exception is important for devices specified for outdoor operation.

Process spread is the larger effect in manufacturing. Two parts from the same wafer can differ in threshold voltage by tens of millivolts, and a voltage chosen to be safe for the slowest part wastes energy on every faster one. Vendors address this with per-part characterisation: a part stores its own operating points in a table programmed at test, and firmware reads the table rather than using a fixed voltage. A design that hard-codes the worst-case voltage pays the worst-case energy on every unit.

Ageing adds a slow drift. Negative bias temperature instability raises threshold voltage over the device’s life, which reduces the maximum frequency at a given voltage. A design with no margin at the start of life can fail years later, and the failure appears first at high temperature. The vendor’s operating points include an ageing margin, which is one of the reasons they are more conservative than a bench measurement suggests.

Where the model stops

The $CV^2f$ model describes dynamic power in a block whose activity factor is constant. Real workloads have activity factors that change with the operating point: a memory-bound loop running at a lower frequency waits less per instruction and therefore has a higher fraction of its energy in the memory system, whose power does not scale with the core’s voltage. The result is that halving the frequency saves less than half the power, and the difference is the memory and bus power that stayed constant.

Leakage is the other term that does not follow the model. It falls with voltage, roughly exponentially, so lowering voltage saves more leakage than dynamic power in a relative sense. On a part where leakage is a large fraction of the total at the top operating point, voltage scaling is more effective than the $V^2$ term alone suggests, and the energy-per-operation minimum sits at a lower voltage than a dynamic-only analysis would place it.

Below the threshold voltage, the subthreshold operating region, the current is exponentially dependent on voltage and the maximum frequency collapses. Some designs use it deliberately for very low throughput work, and the gain is real but the variability is severe: a circuit in subthreshold can vary in speed by an order of magnitude across process and temperature. Using it requires either a very wide timing margin or a mechanism that detects and corrects timing failures, and neither is free.

The final limit is that voltage scaling does not help the parts of the system that are not on the scaled rail. A radio, an analog front end, and an external memory each have their own supply requirements, and the energy they consume is unaffected by the core’s operating point. On a duty-cycled device, the core is often a minority of the budget, and the operating point is a second-order decision behind the sleep schedule described in the duty-cycle arithmetic. The same reasoning applies to the sleep current, which is unaffected by the core’s clock and is set by the state described in what a sleep mode actually turns off.