Successive-Approximation ADCs: Sample-and-Hold Settling and Conversion Timing

A successive-approximation converter resolves an analogue input by binary search in the analogue domain. It captures the input on a capacitor array, then tests it against successively smaller fractions of the reference, setting one bit per test from the most significant down. Twelve bits require twelve comparisons plus the time to acquire the input, and the total is the conversion time. The acquisition phase is where most designs lose accuracy without noticing, because it is the only part of the cycle whose duration depends on the circuit outside the chip.

The capacitor array and what the comparator actually sees

A SAR converter’s heart is a binary-weighted capacitor array. During acquisition, the top plate of the array is connected to the input through a sampling switch, and the bottom plates are tied to a reference. The array charges to the input voltage, and at the end of acquisition the switch opens, freezing the charge on the top plate.

The comparison phase then works by charge redistribution. The controller flips the bottom plate of the largest capacitor from the reference to ground, which shifts the top plate voltage by half the reference. The comparator decides whether the input was above or below that, and the corresponding bit is set or cleared. The next capacitor shifts by a quarter of the reference, then an eighth, and so on.

The accuracy of the result depends on the top plate holding exactly the input voltage at the instant the switch opened. Any charge that the switch’s own capacitance injected as it opened, or any incomplete settling before it opened, becomes an error that no amount of digital post-processing can remove.

The array’s total capacitance is small — on the order of a few picofarads for a twelve-bit converter on a microcontroller — because it is built from the same unit capacitor repeated in binary weights and must fit on the die alongside everything else. That small capacitance is the reason the acquisition phase is sensitive to the source impedance.

The settling time constant

The input path is a series resistance and the array’s capacitance, forming a first-order low-pass network. The source has its own resistance, the sampling switch has an on-resistance of tens to hundreds of ohms, and the array’s capacitance is the load. The time constant is the sum of the resistances times the capacitance.

The path begins at the pad, and the pad’s own configuration is part of it. A pin left in digital input or output mode keeps its input buffer and output driver connected, and both present leakage and capacitance that the analogue measurement sees. Switching the pin to analogue mode disconnects them, which is one of the mode settings described in the GPIO configuration article; a converter channel read through a pin that was never switched reads a value that drifts with the digital activity on neighbouring pins.

Settling to a given accuracy takes a multiple of that time constant. For an error of half a least-significant bit on an N-bit converter, the required number of time constants is approximately ln(2^(N+1)), which is (N+1) × ln 2. For twelve bits that is about 9.0 time constants; for sixteen bits, about 11.8. The requirement grows slowly with resolution but proportionally with the time constant, and the time constant is dominated by whatever is largest.

A source with 10 kilohms of output resistance driving a 4 pF array through a switch of 100 ohms gives a time constant of about 40 ns, so twelve-bit settling needs roughly 360 ns. If the acquisition window is programmed to 3 ADC clock cycles at a 30 MHz clock, that is 100 ns, and the converter samples an input that has not finished settling. The error is not random: it depends on the previous channel’s voltage, so a multiplexer scanning several channels produces crosstalk between adjacent samples rather than noise.

The visible symptom is that a channel reads low when the previous channel was high, and the error shrinks as the acquisition time is extended. That pattern identifies settling as the cause, and it distinguishes it from the other candidate, which is the reference’s own settling or noise.

Sizing the acquisition window

The acquisition time is programmed in ADC clock cycles, and the register field’s width limits the maximum. The value must satisfy the settling requirement for the worst-case source impedance in the design, not the typical one.

t_acq >= (N + 1) * ln(2) * (R_source + R_switch) * C_array

With the numbers above, a 12-bit converter needs about 360 ns. At a 30 MHz ADC clock, one cycle is 33 ns, so the field must be at least 11 cycles, and the next setting the peripheral offers above that is the one to use, which on many parts is 15 cycles and leaves margin for temperature and for the switch resistance rising at low supply voltage.

The conversion time is separate and fixed by the converter’s architecture: twelve bits at one comparison per ADC clock cycle plus a few overhead cycles. The total per-sample time is acquisition plus conversion, and the maximum sample rate is their reciprocal. Lengthening the acquisition window to fix a settling problem lowers the achievable sample rate in proportion to the extra time it adds, which is the trade the design has to accept or avoid by lowering the source impedance.

Lowering the source impedance is usually the cheaper fix. A unity-gain buffer between the source and the pin reduces the effective resistance to the amplifier’s output impedance, which is a few ohms, and the settling requirement collapses. The cost is an extra component, its own offset and drift, and its quiescent current. For a high-impedance sensor such as a photodiode or a thermistor divider, the buffer is often mandatory; for a low-impedance source such as a shunt resistor, the acquisition window can be short.

An external capacitor at the pin helps differently. It does not reduce the source resistance, but it holds charge that the array draws at the sampling instant, so the initial transient is supplied by the capacitor rather than by the source. The capacitor must be large relative to the array’s capacitance — a hundred times larger is a common rule — and it must itself be charged to the input voltage before the sampling switch closes. Its presence changes the settling calculation from a single time constant to a two-time-constant system, and the larger capacitor makes the second one slower. The combination is usually a small series resistor into a larger capacitor at the pin, forming a filter whose cutoff is well above the signal bandwidth and whose charge reservoir is adequate.

Reference and input range

The converter’s output code is a ratio of the input to the reference, so the reference’s accuracy is the measurement’s accuracy. An internal reference on a microcontroller is typically a bandgap with a tolerance of a few percent and a specified drift over temperature, which is adequate for ratiometric measurements and inadequate for absolute ones. An external reference with a tighter tolerance costs a pin and a component and removes the reference from the error budget.

Ratiometric measurement is the case where the reference’s absolute value cancels. If the sensor is a resistive divider excited from the same supply that feeds the reference, both the signal and the reference scale with the supply, and the code depends only on the ratio. A 3.3 V supply that sags to 3.1 V changes both the divider output and the reference by the same factor, and the reading is unchanged. This is why so many sensor circuits are ratiometric: it removes the supply from the error budget at no cost.

The input range is bounded by the reference and by the pin’s own limits. A pin cannot be driven above the supply, and the converter’s input is usually protected by clamping diodes to the supply and ground. Driving a pin above the supply forward-biases the upper clamp and injects current into the supply rail, which can power the whole device through the protection diode and produce a reading that is wrong for reasons unrelated to the converter. The series resistor that limits this current also adds to the source impedance and therefore to the settling requirement, so the two constraints interact.

The multiplexer and the channel-to-channel problem

A converter with an input multiplexer shares one sample-and-hold across several pins. The multiplexer’s on-resistance adds to the source resistance, and the channel switch itself has a capacitance that holds the previous channel’s voltage. When the multiplexer moves to a new channel, that capacitance must be discharged into the new source before the sample is valid.

The settling analysis above applies to the whole path, with the multiplexer’s resistance included. The practical consequence is that a scan of eight channels with one acquisition setting must be sized for the worst channel, and the worst channel is usually the one with the highest source impedance rather than the one with the most interesting signal.

Sampling the same channel twice and discarding the first result is a standard workaround when the acquisition window cannot be extended: the first sample charges the multiplexer’s capacitance to approximately the right value, and the second sample sees an already-settled input. The technique costs a sample slot and works because the error is a function of the voltage difference between consecutive channels, which the first sample largely removes.

Where the datasheet’s numbers come from

The accuracy figures in a converter’s datasheet — integral and differential nonlinearity, offset and gain error — are measured under specific conditions: a particular reference, a particular clock rate, a particular acquisition time, and a source impedance the test circuit defines. The effective number of bits is computed from an FFT of a full-scale sine wave, which means it includes noise and distortion together.

Those conditions are part of the specification, not incidental. A converter specified for twelve bits at a given sample rate achieves twelve bits only when the acquisition window, the source impedance, and the reference meet the test conditions. Shortening the acquisition window to raise the sample rate, or driving the pin from a higher impedance than the test circuit, produces fewer effective bits and no error indication. The converter still returns twelve-bit codes; they are simply codes whose low bits are dominated by settling error.

The distinction between resolution and accuracy is worth keeping explicit. Resolution is the number of bits the converter produces. Accuracy is how close those bits are to the input. A design that needs twelve accurate bits must budget for the acquisition time and the source impedance that twelve bits require, and if the sample rate cannot accommodate both, the resolution should be reduced to ten or eight bits so that the conversion time and acquisition window fit. Throwing away the low bits in software after the fact does not recover the accuracy, because the error is in the sampled charge, not in the digital representation. The timer that paces those conversions is the subject of the timer arithmetic article, and the two budgets have to be computed together.