Tag
adc
- Nov 11, 2025 Successive-Approximation ADCs: Sample-and-Hold Settling and Conversion Timing What limits the sample rate of a SAR converter, why the sampling switch needs a settling budget, and how source impedance turns a datasheet accuracy figure into a smaller one. embedded systems
- May 6, 2024 Quantization Step Size, the Six-Decibel Rule, and Dither Why each added bit buys roughly six decibels of signal-to-noise ratio, when the uniform-error model stops holding, and what dither trades away to fix it. scientific computing