Embedded Systems · Cluster
Bare-Metal Programming
Startup code, vectors, and register access.
- 01 Where the Reset Vector and Initial Stack Pointer Come From Why the first two words of a firmware image are read by hardware before any instruction executes, how the vector table is indexed, and what breaks when the table moves.
- 02 Getting Initialised Data and BSS Ready Before main Runs Why a C static variable occupies two addresses, how the startup copy moves initialised data from flash into RAM, and why zeroed memory has to be zeroed by software.
- 03 What volatile Guarantees in Memory-Mapped Register Access volatile forces a compiled access to happen, but it does not make the access atomic, ordered, or visible to the device in the order the source implies.
- 04 Read-Modify-Write Hazards in Peripheral Registers Why assigning through a bit-set idiom corrupts registers the hardware also writes, how write-one-to-clear flags interact with that idiom, and what surrogate registers buy.
- 05 What the Hardware Does Between an Interrupt and Its Handler The stacked frame, the link register value that redirects the return, and the chaining shortcuts that make back-to-back interrupts cheap.
- 06 Relocating the Vector Table and Running It from RAM How the table base register changes where exceptions dispatch, why a misaligned base fails silently, and what a writable copy of the table enables.
- 07 Masking Interrupts, Priorities, and Exclusive Access Without an OS The three mechanisms a bare-metal core offers for making a shared update atomic, what each one costs, and how to pick between them per invariant.
- 08 Ordering Constraints in the First Thousand Instructions Clock sources, flash wait states, external memory controllers, and the floating-point unit all have prerequisites, so the startup sequence is a dependency graph rather than a list.
- 09 Scheduling Without a Scheduler: Superloops and Their Latency Budget How a main loop plus interrupt handlers bounds worst-case response time, where jitter creeps in, and the point at which the structure stops meeting its deadlines.
- 10 Fault Escalation and Reading the Stacked Frame After a Crash Why an imprecise bus fault arrives as a hard fault, which status bits distinguish the causes, and how the stacked frame locates the instruction that failed.