Power Delivery Network Impedance and the Target It Must Hold

A rail is specified as a voltage with a tolerance. The tolerance is what the load’s circuits need in order to work: a core supply of 1.0 V ±5% must stay between 0.95 V and 1.05 V at the die, including every transient the load itself generates. The power delivery network is the impedance between the regulator’s sense point and the die, and the design problem is to make that impedance low enough across the band where the load draws transient current that the voltage stays inside the window.

Deriving the target impedance

The load’s current step is the input. A processor that draws 20 A at full activity and 8 A at idle presents a 12 A step with a rise time set by its own clocking and power management, perhaps a few hundred nanoseconds. The voltage disturbance produced by that step is the step amplitude multiplied by the impedance the network presents at the frequencies contained in the step.

The flat-band target is therefore

$$Z_{target} = \frac{V_{rail} \times \text{tolerance fraction}}{\Delta I}$$

For a 1.0 V rail with 5% tolerance and a 12 A step, the target is about 4 mΩ. For a 3.3 V peripheral rail with the same tolerance and a 1 A step, it is 165 mΩ. The difference of more than an order of magnitude explains why processor rails get entire design efforts and peripheral rails get a few capacitors: the target scales with tolerance and inversely with current, and core rails have both the tightest tolerance and the largest current.

The flat-band target is not the whole specification. The network’s impedance is a function of frequency, and it must stay under the target only over the band where the load actually draws transient current. Above the point where the die’s own on-package capacitance takes over, the board does not need to supply anything. That upper frequency is set by the package and the die, not by the board, and it is typically in the tens to hundreds of megahertz range for a large processor.

What sets the impedance at each frequency

The network is a cascade of elements, each dominant in its own band.

At the lowest frequencies the voltage regulator controls the impedance through its feedback loop. A regulator with adequate loop bandwidth presents an output impedance of a few milliohms up to the frequency where its gain falls to unity. Below that, the regulator behaves as a controlled source and the impedance is set by the loop, not by the capacitors.

Above the regulator’s bandwidth the bulk capacitors take over. Large electrolytic or polymer parts with tens to hundreds of microfarads have enough capacitance to hold the rail through a load step lasting microseconds, and their ESR sets the impedance floor in that band. Their inductance is irrelevant at those frequencies.

Higher still, the ceramic decoupling network dominates. Each capacitor is a series RLC with a self-resonant frequency where its impedance is minimum and equal to its ESR; above resonance it looks inductive. A 100 nF 0402 ceramic has a self-resonant frequency in the ten-to-thirty megahertz range; a 10 µF part of the same size resonates lower. The network’s job is to place enough capacitors of the right values so that the combined impedance stays low across the band, and the parallel combination of many parts reduces both the ESR and the ESL by the number of parts.

At the top of the board’s range the plane capacitance between power and ground planes contributes. Two planes separated by 0.1 mm of FR-4 give a capacitance of about 0.4 pF per square millimetre, so a 100 mm by 100 mm pair gives roughly 4 nF. That is a small capacitance compared with the ceramic bank, but it has essentially no inductance, so it behaves well at the highest board frequencies where every discrete part has already turned inductive.

Mounting inductance is the part that is usually wrong

A capacitor’s datasheet impedance curve assumes the part is connected to an ideal source and load. On a board it is connected through a footprint, a pair of vias, and a length of plane. That path has inductance of its own, and it is in series with the capacitor.

The numbers are unforgiving. A via through a 1.6 mm board is roughly 1 nH. A capacitor placed 5 mm from the load, with its current path running along a trace rather than a plane, adds several nanohenries. At 100 MHz, 1 nH is 0.63 Ω of reactance, which is larger than the target impedance of a core rail by more than two orders of magnitude.

The consequence is that the capacitor network’s effectiveness is limited by how the parts are mounted, not by how many are placed. Two design rules follow directly. The first is to place the small-value capacitors as close to the load as the fanout allows, and to connect them to the planes with vias rather than traces, because a via’s inductance is lower than a trace’s for the same distance. The second is to put the via pair — power and ground — as close together as the footprint permits, so that the loop between them is small. Two vias 1 mm apart carrying opposite currents have a much lower loop inductance than two vias 5 mm apart.

import math

def z_cap(c_f, esl_h, esr_ohm, f_hz):
    w = 2 * math.pi * f_hz
    x = w * esl_h - 1 / (w * c_f)
    return complex(esr_ohm, x)

def z_parallel(parts, c_f, esl_h, esr_ohm, f_hz):
    z = z_cap(c_f, esl_h, esr_ohm, f_hz)
    return z / parts        # identical parts in parallel divide by count

# 20 x 100 nF 0402 ceramics, 0.9 nH mounted (part plus vias), 4 mOhm each
for f_mhz in (1, 10, 50, 200):
    z = z_parallel(20, 100e-9, 0.9e-9, 0.004, f_mhz * 1e6)
    print(f"{f_mhz:4d} MHz  |Z| = {abs(z)*1000:7.2f} mOhm")

The output shows the shape that matters: the impedance falls as the network’s capacitance takes over, reaches a minimum at the parallel resonance of capacitance and inductance, and then rises as the inductance dominates. Adding more of the same part lowers the whole curve but does not move its shape.

Anti-resonance between capacitor groups

Mixing values creates a problem that a single value does not have. A bank of small capacitors looks capacitive below its resonance and inductive above it. A bank of large capacitors looks inductive over the range where the small ones are still capacitive. In parallel, the inductance of one group and the capacitance of the other form a parallel resonant circuit, and at that frequency the impedance rises sharply — an anti-resonance peak.

The peak can be much higher than either group’s own impedance, and if it lands where the load draws current, the rail voltage rings at that frequency. The standard mitigations are to use values close enough that their resonances overlap, to damp the peak with a resistor or with a capacitor whose ESR is deliberately not the minimum available, and to place the groups so that the anti-resonance is pushed above the band of interest.

Damping is the part that is often skipped. A capacitor bank with very low ESR is excellent at its own resonance and poor everywhere else, because a high-Q parallel resonance has a high peak. Some designs deliberately choose a part with a few milliohms of ESR for the bulk position so that the anti-resonance is flattened, which is the same trade as adding a series resistor to a resonant circuit.

Measuring the network instead of simulating it

The impedance curve can be computed from a model, but the model’s accuracy at the frequencies that matter depends on parasitics that are hard to extract: via inductance, plane spreading inductance, and the load’s own package. The practical check is a two-port measurement on the assembled board.

A vector network analyser with one port connected across the rail at the load and the other at the regulator, or a single-port measurement of the rail’s impedance with the board unpowered, gives the curve directly. The measurement requires care: the probe’s own inductance is in the path, the ground connection must be short, and on an unpowered board the load’s junction capacitances are part of what is being measured, so the curve includes the die as well as the network.

An alternative that requires less equipment is a step-load test: a MOSFET switched across the rail draws a current step, and an oscilloscope with adequate bandwidth records the voltage deviation. The recorded waveform contains the network’s response to a known excitation, and its ringing frequency identifies the resonance that dominates. The amplitude of the deviation compared with the target gives the margin. Unlike the network-analyser measurement, this one can only be run on a board that is already alive, so the rails must come on in the order the devices demand first; the sequence in Power Sequencing, Reset Order, and the First Power-On is the prerequisite.

The measurement is limited by the probe. A scope probe with a ground lead of several centimetres has enough inductance to see its own resonance, so the deviation it reports may be the probe’s rather than the board’s. The probing problem is the same one that affects every high-speed measurement, and it is treated in Probing High-Speed Nets Without Measuring the Probe.

Where the board’s responsibility ends

The board supplies the rail up to the package. Above that frequency the package’s own decoupling and the die’s capacitance take over, and the board’s contribution is a small part of the total. A design that meets its target impedance up to the package’s band and no further is doing its job; a design that tries to extend the board’s range by adding more capacitors is fighting a losing battle against the mounting inductance.

The transition between the board and the package is the connector or the solder balls, and that interface has its own inductance. It is the reason the target impedance is usually specified at the package’s pins rather than at the die, and the reason the load’s current step is specified with the package in place. The board design and the package design are one problem split across two organisations, and the split point is where the impedance budget is allocated.

The DC path matters as much as the AC one. A plane carrying 20 A has a resistance that produces a DC drop, and a plane 0.1 mm thick with a narrow neck at a connector can produce tens of millivolts that eat directly into the tolerance window. The DC drop and the AC impedance are separate budgets that share the same tolerance, and both must be checked before the rail is considered done.