Topic domain
Hardware Engineering
Digital logic, boards, and the physical substrate.
- Articles
- 80
- Clusters
- 8
- Foundational
- 24
- Intermediate
- 32
- Advanced
- 24
Gates, flip-flops, and combinational design.
- How a CMOS Gate Computes with Pull-Up and Pull-Down Networks
- Canonical Forms, Minterms, and the Cost of Two-Level Logic
- Two-Level Minimization with Prime Implicants and the Quine-McCluskey Method
- Combinational Hazards and Why Consensus Terms Eliminate Glitches
- Multiplexers, Decoders, and Shannon Expansion as Logic Realization
- Latches, Flip-Flops, and What Edge Sensitivity Actually Means
Hardware description and mapping to silicon.
- Delta Cycles and the Stratified Event Queue in HDL Simulation
- Blocking and Non-Blocking Assignment: What Each Maps To in Silicon
- Inferred Latches: Why an Incomplete Branch Becomes State
- State Encoding: Why the Same State Machine Can Cost Three Flops or Eight
- Technology Mapping: Covering a Boolean Network With Library Cells
- Setup and Hold Slack: Reading a Static Timing Report
FPGAs
10Reconfigurable fabric, timing closure, and tooling.
- Lookup Tables, Carry Chains, and the Routing Fabric
- Block RAM Primitives and Memory Inference from RTL
- Clock Networks, Global Buffers, and Skew Budgets
- Static Timing Analysis: Slack, Corners, and Uncertainty
- Timing Constraints: Clock Definitions, Groups, and Exceptions
- Clock Domain Crossing: Synchronizers, Handshakes, and False Paths
PCIe, memory channels, and topology.
- Shared-Bus Arbitration and the Clock Ceiling That Ended It
- PCIe Lanes and the Three Layers That Carry a Transaction
- PCIe Topology and Bus-Device-Function Enumeration
- Memory Channel Interleaving and the Granularity Trade
- Posted Writes and the Ordering Rules a Device Must Respect
- Device DMA Addressing and What the IOMMU Changes
Delivery, dissipation, and throttling.
- The Power Delivery Chain from Wall Adapter to Core Rail
- Decoupling Capacitors and the Impedance of a Power Distribution Network
- Multiphase Buck Converters and Where Regulator Efficiency Goes
- Static IR Drop and Dynamic Droop Inside the Die Power Grid
- Junction Temperature and the Thermal Resistance Network
- Heat Pipes and Vapor Chambers: Moving Heat by Phase Change
NAND, HDD mechanics, and controllers.
- How a NAND Cell Stores a Bit: Threshold Voltage and Read Levels
- Writing and Reading a Magnetic Bit on a Spinning Platter
- Page Program and Block Erase: The Asymmetry That Shapes Flash Software
- Seek Time, Rotational Latency, and Why the Average Is Not the Middle
- Error Correction in NAND: From Hard Bits to Soft Read Retry
- Flash Translation Layers: Mapping Tables, Garbage Collection, and Write Cost
Board Design
10Signal integrity, layout, and bring-up.
- Return Current Paths and Why Loop Area Sets Trace Inductance
- Rise Time, Electrical Length, and When a Trace Stops Being a Wire
- Characteristic Impedance from Stackup Geometry
- Termination Topologies and the Reflection They Absorb
- Crosstalk: Mutual Capacitance, Mutual Inductance, and Coupling Length
- Via Transitions, Stubs, and Backdrilling
Fabrication, yield, and test.
- The Unit Step of Fabrication: Lithography, Etch, and Deposition
- Design Rules as an Encoding of Process Limits
- Process Corners and Why Timing Sign-off Is a Set of Scenarios
- Yield Models That Turn Defect Density into Die Cost
- Scan Chains and Automatic Test Pattern Generation
- Wafer Probe and the Economics of Test Coverage
All Hardware Engineering articles
- Oct 23, 2026 Setup and Hold Slack: Reading a Static Timing Report How arrival and required times are propagated through a timing graph, why setup and hold checks run in opposite directions, and how skew, derating, and path exceptions change the verdict.
- Oct 7, 2026 Seek Time, Rotational Latency, and Why the Average Is Not the Middle How a drive decomposes an access into seek, settle, and rotation, why the mean seek is not half the maximum, and how queueing turns latency into a throughput number.
- Oct 4, 2026 Non-Transparent Bridges and Multi-Host PCIe Topologies Why two root complexes cannot simply be cabled together, how a non-transparent bridge presents a translated address window to each side, and what the doorbell handshake does not guarantee.
- Sep 16, 2026 Posted Writes and the Ordering Rules a Device Must Respect Why PCIe memory writes are fire-and-forget, which transactions may pass which, and how a device orders its data ahead of its interrupt so the handler sees a completed transfer.
- Sep 8, 2026 Inferred Latches: Why an Incomplete Branch Becomes State How a combinational block that fails to assign its output on every path forces the synthesis tool to infer a level-sensitive latch, and which coding shapes create that condition.
- Sep 3, 2026 Error Correction in NAND: From Hard Bits to Soft Read Retry How BCH and LDPC codes absorb the raw bit error rate of a flash page, why soft-decision decoding needs several reads at shifted reference voltages, and what happens when correction runs out.
- Aug 27, 2026 The Unit Step of Fabrication: Lithography, Etch, and Deposition How one patterned layer is built on a wafer: resist coating, exposure through a reduced reticle, development, etch or implant, and the overlay budget that ties every layer to the one below it.
- Aug 18, 2026 Canonical Forms, Minterms, and the Cost of Two-Level Logic How any Boolean function is written as a sum of minterms or product of maxterms, and why literal count is the currency that minimization tries to spend.
- Aug 6, 2026 State Encoding: Why the Same State Machine Can Cost Three Flops or Eight How binary, one-hot, and Gray encodings trade register bits against next-state logic depth, and why the encoding chosen in code is not necessarily the encoding built.
- Jul 25, 2026 Clock Domain Crossing: Synchronizers, Handshakes, and False Paths Why a flip-flop sampling an unrelated clock can go metastable, how a two-flop synchronizer bounds the failure rate, and how data buses cross domains without tearing.
- Jul 14, 2026 Static Timing Analysis: Slack, Corners, and Uncertainty How a timing graph is built from the netlist, what setup and hold slack mean at the two ends of a path, and why the report is only as trustworthy as its corner and derate assumptions.
- Jul 6, 2026 Lookup Tables, Carry Chains, and the Routing Fabric How a configurable logic cell implements arbitrary Boolean functions from SRAM bits, why adders get a dedicated carry path, and why interconnect rather than logic sets the achievable frequency.
- Jul 3, 2026 Delta Cycles and the Stratified Event Queue in HDL Simulation Why an event-driven simulator orders zero-delay updates by region rather than by source text, how combinational feedback stalls simulated time, and which races the queue does not prevent.
- Jun 20, 2026 Energy-Optimal Operating Points and the Shape of DVFS Why the lowest voltage a circuit can run at is not the most efficient one, how frequency and voltage must move together, and where the energy minimum sits for a real workload.
- Jun 7, 2026 Flash Translation Layers: Mapping Tables, Garbage Collection, and Write Cost How a controller maps logical blocks onto pages that can never be overwritten, why the mapping table does not fit in SRAM, and how the choice of victim block sets write amplification.
- Jun 6, 2026 Power Sequencing, Reset Order, and the First Power-On Why rails must rise in a defined order, what happens to a device whose I/O is driven before its supply, and how boundary scan turns a dead board into a locatable fault.
- Jun 3, 2026 Equivalence Checking: Proving a Netlist Matches Its RTL How combinational equivalence is reduced to a miter of two circuits and a satisfiability question, why sequential transformations break that reduction, and where the proof stops being cheap.
- May 31, 2026 Yield Models That Turn Defect Density into Die Cost The Poisson and negative binomial yield formulas, why clustering makes the Poisson model pessimistic, and how die area, redundancy, and wafer size set the cost of a working part.
- May 20, 2026 How Power Density and Pin Count Decide the Package How power density, inductance, and thermal expansion decide between wire bond, flip-chip, and wafer-level packaging, and which of the three is usually the binding constraint.
- May 15, 2026 Design Rules as an Encoding of Process Limits Why a process rule deck is layer-pair specific, how width, spacing, and enclosure numbers derive from lithography and etch capability, and what a design rule checker can and cannot prove about a layout.
- Apr 29, 2026 Rise Time, Electrical Length, and When a Trace Stops Being a Wire The criterion that separates a lumped connection from a transmission line, how dielectric constant sets propagation delay, and why slow edges on long traces still misbehave.
- Apr 27, 2026 How a NAND Cell Stores a Bit: Threshold Voltage and Read Levels The floating-gate transistor, the programmed charge that shifts its threshold, and why adding levels to a cell shrinks the margin every read decision depends on.
- Apr 25, 2026 Writing and Reading a Magnetic Bit on a Spinning Platter How a write head sets the direction of magnetisation in a granular medium, why transitions rather than levels carry the data, and what the read sensor and channel must recover.
- Apr 16, 2026 Junction Temperature and the Thermal Resistance Network How a die's temperature is computed from ambient through a series of thermal resistances, what each interface contributes, and why the transient curve differs from the steady-state number.
- Apr 8, 2026 Burn-In, Lifetime Models, and the Bathtub Curve Why a fraction of dies fail early and separately from wear-out, how Arrhenius voltage and temperature acceleration are used to compress a lifetime into a test, and what burn-in costs.
- Apr 4, 2026 Thermal Throttling: Duty Cycles, Ratio Capping, and Power Limits How a processor detects that it is too hot or drawing too much, which of several limiters acts first, and what each one does to frequency, voltage, and the workload's timing.
- Feb 27, 2026 Placement, Routing, and Congestion in the Logic Array How the placer decides where each cell goes, how the router allocates wire segments, and why a design can fail to route while the array looks half empty.
- Feb 24, 2026 Differential Pairs and the Cost of Asymmetry How intra-pair skew converts differential signal into common mode, how to derive a length-matching tolerance from a skew budget, and why the two modes propagate at different speeds.
- Feb 20, 2026 Memory Redundancy and Repair: Turning Defective Arrays into Working Parts How spare rows and columns, fuse or antifuse programming, and built-in self-repair convert a memory array with dozens of defects into a passing die, and when the spare budget runs out.
- Jan 27, 2026 PCIe Topology and Bus-Device-Function Enumeration How a host walks a tree of bridges and switches, how each function is named by bus, device, and function number, and why configuration space is a per-function address space.
- Jan 26, 2026 How a CMOS Gate Computes with Pull-Up and Pull-Down Networks The transistor network behind a static CMOS gate, how the voltage transfer characteristic defines noise margins, and why stack height limits fan-in.
- Jan 20, 2026 Power-Loss Protection: What a Controller Must Persist, and When The in-flight state a flash controller holds in volatile memory, the energy budget that keeps it alive long enough to flush, and how recovery reconstructs a mapping table from torn pages.
- Jan 16, 2026 Multiphase Buck Converters and Where Regulator Efficiency Goes How interleaved buck phases divide a hundred-ampere load, why ripple cancellation lets the inductors shrink, and which loss terms set the efficiency curve.
- Jan 14, 2026 Page Program and Block Erase: The Asymmetry That Shapes Flash Software Why a flash array writes in pages of a few kilobytes but can only be cleared in blocks of hundreds, what that costs in area and time, and how the asymmetry propagates upward.
- Dec 8, 2025 Link Training and the Width a PCIe Link Settles On What the link state machine exchanges before a single packet moves, how width and lane ordering are agreed, and why a link can train down to a fraction of its slot capability.
- Nov 21, 2025 PCIe Lanes and the Three Layers That Carry a Transaction How a PCIe transaction is assembled from transaction layer packets, sequence-numbered data link packets, and physical layer symbols across one or more lanes.
- Nov 6, 2025 Clock Domain Crossing: Synchronizers, Handshakes, and Asynchronous FIFOs Why a signal crossing between unrelated clocks cannot be checked by static timing, and the three structures that carry data across a boundary safely.
- Oct 30, 2025 Combinational Hazards and Why Consensus Terms Eliminate Glitches How unequal path delays produce output pulses in a logically correct circuit, how static and dynamic hazards differ, and when adding redundant logic is the fix.
- Oct 30, 2025 Leakage Power and the Electrothermal Feedback Loop Why subthreshold and gate leakage rise exponentially with temperature, how that turns the power budget into a positive feedback loop, and where the loop stabilises or runs away.
- Oct 28, 2025 Scan Chains and Automatic Test Pattern Generation Why a flip-flop becomes a two-mode scan cell, how a stuck-at fault model turns testing into a search for input patterns, and what the ATPG tool trades away when it cannot fill the vector.
- Oct 23, 2025 Metastability: What a Two-Flop Synchronizer Buys and What It Cannot Why a flip-flop that samples a changing asynchronous input can hover between logic levels, how the resolution failure rate falls exponentially with the time allowed, and why buses cannot be crossed one bit at a time.
- Oct 10, 2025 Static IR Drop and Dynamic Droop Inside the Die Power Grid Why the last hundred millivolts of a processor's supply budget is spent in on-die metal, how current transients turn grid inductance into voltage droop, and where electromigration sets the hard limit.
- Oct 8, 2025 Block RAM Primitives and Memory Inference from RTL How dedicated memory blocks are structured internally, why inference from an array declaration produces different hardware than instantiation, and how read-during-write behaviour decides correctness.
- Sep 24, 2025 State Encoding and Next-State Logic in a Finite-State Machine How the choice between binary, one-hot, and Gray encoding moves cost between flip-flops and decode logic, and why unused encodings are a reliability problem.
- Sep 15, 2025 Shared-Bus Arbitration and the Clock Ceiling That Ended It How a multiplexed parallel bus runs one transaction at a time, how a central arbiter decides which master owns the wires, and which electrical limits forced the move to point-to-point links.
- Sep 10, 2025 Technology Mapping: Covering a Boolean Network With Library Cells How synthesis chooses cells from a standard-cell library to implement an optimized gate network, why the choice is iterative once real loads and slews enter the cost, and what fanout limits force into the netlist.
- Sep 3, 2025 High-Level Synthesis: Scheduling, Binding, and the Latency-Area Trade How a C-level description becomes a datapath through dependency scheduling and resource binding, why the loop and array decisions dominate the result, and where the generated hardware diverges from the source.
- Aug 21, 2025 Wafer Probe and the Economics of Test Coverage How a probe card makes contact with pads a few tens of micrometres wide, why test time is a fab cost, and how the choice of coverage trades probe cost against escape rate and package cost.
- Aug 17, 2025 Two-Level Minimization with Prime Implicants and the Quine-McCluskey Method How adjacent minterms merge into prime implicants, how don't-care rows change the cover, and why exact minimization becomes intractable past a handful of inputs.
- Aug 6, 2025 Blocking and Non-Blocking Assignment: What Each Maps To in Silicon How the two assignment forms differ in when they update their target, why one models a wire and the other a flip-flop, and where mixing them produces a simulation that does not match the netlist.
- Aug 6, 2025 Power Delivery Network Impedance and the Target It Must Hold How a target impedance is derived from a rail voltage and current step, why the capacitor network has anti-resonances, and where mounting inductance defeats the parts on the schematic.
- Aug 6, 2025 Protection Information: Eight Bytes That Catch Misdirected Writes How T10 protection information appends a CRC, a reference tag, and an application tag to every logical block, and what it costs to check them at the drive and at the host.
- Jul 24, 2025 SR-IOV and How One Device Becomes Many Functions How a physical function creates lightweight virtual functions with their own configuration space and requester IDs, and why function-level isolation is not resource isolation.
- May 5, 2025 Clock Networks, Global Buffers, and Skew Budgets Why a clock reaches every register through a dedicated balanced tree, what skew and jitter cost a timing budget, and when a clock must be routed on general interconnect instead.
- Apr 30, 2025 Fan Curves, System Impedance, and Where a Cooler Actually Operates How a fan's pressure-flow curve intersects the chassis impedance curve to fix the operating point, and why the resulting airflow determines the heat sink's resistance.
- Mar 18, 2025 The Power Delivery Chain from Wall Adapter to Core Rail How a processor's sub-volt, hundred-ampere supply is produced from a 12 V input, why every conversion stage loses a share, and where the losses accumulate.
- Mar 7, 2025 Clock Skew, Jitter, and the Synchronous Timing Budget The two inequalities that decide whether a synchronous design works, how skew helps setup and hurts hold, and why clock distribution is a first-class design problem.
- Feb 8, 2025 Flit Mode and PAM4: How PCIe Reached 64 GT/s Why the next rate step required four signal levels instead of two, why that forces forward error correction into the physical layer, and what fixed-size flits replace.
- Dec 26, 2024 Process Corners and Why Timing Sign-off Is a Set of Scenarios How transistor speed and interconnect parasitics are bounded by slow, fast, and nominal process corners, temperature, and voltage, and why static timing analysis closes each combination separately.
- Nov 13, 2024 Channels, Dies, and Planes: How a Flash Controller Reaches Its Throughput A single flash die serves one operation at a time, so drive throughput comes from concurrency across channels and planes; the arithmetic of that concurrency sets the queue depth a workload needs.
- Nov 12, 2024 Latches, Flip-Flops, and What Edge Sensitivity Actually Means How a cross-coupled pair stores a bit, why a master-slave arrangement turns level sensitivity into edge triggering, and what transparency costs downstream.
- Nov 4, 2024 Timing Constraints: Clock Definitions, Groups, and Exceptions How a constraint file tells the timing engine what the clocks are and which paths matter, and why an over-generous false path is a correctness bug rather than an optimization.
- Oct 5, 2024 Setup and Hold Time, Metastability, and the Two-Flop Synchronizer Why a flip-flop needs its input stable around the clock edge, how a near-threshold sample resolves probabilistically, and how cascaded flops bound the failure rate.
- Jul 9, 2024 Memory Channel Interleaving and the Granularity Trade Why physical addresses are striped across memory channels at cache-line granularity, how the hash decides which channel owns an address, and what that choice costs for sequential and strided access.
- Jun 27, 2024 Crosstalk: Mutual Capacitance, Mutual Inductance, and Coupling Length The two coupling mechanisms that inject noise into a neighbouring trace, why near-end and far-end crosstalk behave differently, and how spacing and layer choice change the balance.
- Jun 22, 2024 Retiming, Pipelining, and Register Balancing in the Fabric How moving registers across combinational logic changes which resources a path traverses, why the fabric makes retiming cheaper than in an ASIC, and where the technique stops helping.
- May 17, 2024 Register Retiming: Moving Flip-Flops Across Combinational Logic How a retiming tool redistributes registers along a path without changing the function, what the legal moves are, and why the resulting netlist no longer matches the RTL that was written.
- Apr 19, 2024 Decoupling Capacitors and the Impedance of a Power Distribution Network Why a regulator cannot supply a load that changes in nanoseconds, how a network of capacitors is chosen to hold a target impedance across frequency, and where the anti-resonances come from.
- Apr 15, 2024 Shingled Magnetic Recording and the Write Cursor Why overlapping written tracks raise areal density, how that turns every random write into a band rewrite, and what a zoned interface has to expose to make the constraint usable.
- Dec 12, 2023 Partial Reconfiguration: Static and Dynamic Partitions How a region of an FPGA is redefined while the rest keeps running, what the boundary between static and dynamic logic requires, and why the decoupler is not optional.
- Sep 19, 2023 Multiplexers, Decoders, and Shannon Expansion as Logic Realization Why a 2-to-1 multiplexer can implement any function once its data inputs are tied to constants, and how decoder-and-OR structures realize sum-of-products forms.
- Aug 30, 2023 High-Level Synthesis: Scheduling, Binding, and Inferred Hardware How a C function becomes a datapath, why the clock period constraint drives scheduling decisions, and what the interface protocol synthesis chooses on the designer's behalf.
- Jul 6, 2023 Device DMA Addressing and What the IOMMU Changes How a device names memory without access to the CPU page tables, why 32-bit DMA needs bounce buffers, and how an IOMMU translates device addresses per requester.
- Apr 28, 2023 Probing High-Speed Nets Without Measuring the Probe Why a scope probe loads the node it measures, how ground-lead inductance dominates above a few hundred megahertz, and which probing methods keep the measurement honest.
- Mar 30, 2023 Return Current Paths and Why Loop Area Sets Trace Inductance Why the return current of a high-speed signal crowds beneath its trace, what a broken reference plane does to that path, and how loop area translates into ground bounce.
- Mar 10, 2023 Via Transitions, Stubs, and Backdrilling Why a plated through-hole behaves as a lumped discontinuity, how the unused barrel becomes a resonant stub, and what backdrilling and antipad sizing actually remove.
- Nov 15, 2022 Characteristic Impedance from Stackup Geometry How trace width, dielectric height, and copper thickness combine into a characteristic impedance, why the equations are approximations, and what happens to impedance when a net changes layer.
- Sep 9, 2022 Termination Topologies and the Reflection They Absorb Series, parallel, Thevenin, and active termination compared by what they do to the incident wave, what they cost in DC current, and where each one fails on a multi-drop bus.
- Mar 30, 2022 Known-Good-Die and the Trust Problem in Multi-Die Assembly Why assembling individually working dies does not produce a working module, what a stack test standard can and cannot verify, and what must move on-die to make multi-die packages economical.
- Nov 30, 2021 Heat Pipes and Vapor Chambers: Moving Heat by Phase Change How a sealed wick structure transports heat with a temperature drop far smaller than copper conduction, and which of the four transport limits binds first in a processor cooler.