Hardware Engineering · Cluster
Buses and Interconnects
PCIe, memory channels, and topology.
- 01 Shared-Bus Arbitration and the Clock Ceiling That Ended It How a multiplexed parallel bus runs one transaction at a time, how a central arbiter decides which master owns the wires, and which electrical limits forced the move to point-to-point links.
- 02 PCIe Lanes and the Three Layers That Carry a Transaction How a PCIe transaction is assembled from transaction layer packets, sequence-numbered data link packets, and physical layer symbols across one or more lanes.
- 03 PCIe Topology and Bus-Device-Function Enumeration How a host walks a tree of bridges and switches, how each function is named by bus, device, and function number, and why configuration space is a per-function address space.
- 04 Memory Channel Interleaving and the Granularity Trade Why physical addresses are striped across memory channels at cache-line granularity, how the hash decides which channel owns an address, and what that choice costs for sequential and strided access.
- 05 Posted Writes and the Ordering Rules a Device Must Respect Why PCIe memory writes are fire-and-forget, which transactions may pass which, and how a device orders its data ahead of its interrupt so the handler sees a completed transfer.
- 06 Device DMA Addressing and What the IOMMU Changes How a device names memory without access to the CPU page tables, why 32-bit DMA needs bounce buffers, and how an IOMMU translates device addresses per requester.
- 07 Link Training and the Width a PCIe Link Settles On What the link state machine exchanges before a single packet moves, how width and lane ordering are agreed, and why a link can train down to a fraction of its slot capability.
- 08 Flit Mode and PAM4: How PCIe Reached 64 GT/s Why the next rate step required four signal levels instead of two, why that forces forward error correction into the physical layer, and what fixed-size flits replace.
- 09 Non-Transparent Bridges and Multi-Host PCIe Topologies Why two root complexes cannot simply be cabled together, how a non-transparent bridge presents a translated address window to each side, and what the doorbell handshake does not guarantee.
- 10 SR-IOV and How One Device Becomes Many Functions How a physical function creates lightweight virtual functions with their own configuration space and requester IDs, and why function-level isolation is not resource isolation.