Hardware Engineering · Cluster
FPGAs
Reconfigurable fabric, timing closure, and tooling.
- 01 Lookup Tables, Carry Chains, and the Routing Fabric How a configurable logic cell implements arbitrary Boolean functions from SRAM bits, why adders get a dedicated carry path, and why interconnect rather than logic sets the achievable frequency.
- 02 Block RAM Primitives and Memory Inference from RTL How dedicated memory blocks are structured internally, why inference from an array declaration produces different hardware than instantiation, and how read-during-write behaviour decides correctness.
- 03 Clock Networks, Global Buffers, and Skew Budgets Why a clock reaches every register through a dedicated balanced tree, what skew and jitter cost a timing budget, and when a clock must be routed on general interconnect instead.
- 04 Static Timing Analysis: Slack, Corners, and Uncertainty How a timing graph is built from the netlist, what setup and hold slack mean at the two ends of a path, and why the report is only as trustworthy as its corner and derate assumptions.
- 05 Timing Constraints: Clock Definitions, Groups, and Exceptions How a constraint file tells the timing engine what the clocks are and which paths matter, and why an over-generous false path is a correctness bug rather than an optimization.
- 06 Clock Domain Crossing: Synchronizers, Handshakes, and False Paths Why a flip-flop sampling an unrelated clock can go metastable, how a two-flop synchronizer bounds the failure rate, and how data buses cross domains without tearing.
- 07 Retiming, Pipelining, and Register Balancing in the Fabric How moving registers across combinational logic changes which resources a path traverses, why the fabric makes retiming cheaper than in an ASIC, and where the technique stops helping.
- 08 Placement, Routing, and Congestion in the Logic Array How the placer decides where each cell goes, how the router allocates wire segments, and why a design can fail to route while the array looks half empty.
- 09 High-Level Synthesis: Scheduling, Binding, and Inferred Hardware How a C function becomes a datapath, why the clock period constraint drives scheduling decisions, and what the interface protocol synthesis chooses on the designer's behalf.
- 10 Partial Reconfiguration: Static and Dynamic Partitions How a region of an FPGA is redefined while the rest keeps running, what the boundary between static and dynamic logic requires, and why the decoupler is not optional.