Hardware Engineering · Cluster
HDL and Synthesis
Hardware description and mapping to silicon.
- 01 Delta Cycles and the Stratified Event Queue in HDL Simulation Why an event-driven simulator orders zero-delay updates by region rather than by source text, how combinational feedback stalls simulated time, and which races the queue does not prevent.
- 02 Blocking and Non-Blocking Assignment: What Each Maps To in Silicon How the two assignment forms differ in when they update their target, why one models a wire and the other a flip-flop, and where mixing them produces a simulation that does not match the netlist.
- 03 Inferred Latches: Why an Incomplete Branch Becomes State How a combinational block that fails to assign its output on every path forces the synthesis tool to infer a level-sensitive latch, and which coding shapes create that condition.
- 04 State Encoding: Why the Same State Machine Can Cost Three Flops or Eight How binary, one-hot, and Gray encodings trade register bits against next-state logic depth, and why the encoding chosen in code is not necessarily the encoding built.
- 05 Technology Mapping: Covering a Boolean Network With Library Cells How synthesis chooses cells from a standard-cell library to implement an optimized gate network, why the choice is iterative once real loads and slews enter the cost, and what fanout limits force into the netlist.
- 06 Setup and Hold Slack: Reading a Static Timing Report How arrival and required times are propagated through a timing graph, why setup and hold checks run in opposite directions, and how skew, derating, and path exceptions change the verdict.
- 07 Metastability: What a Two-Flop Synchronizer Buys and What It Cannot Why a flip-flop that samples a changing asynchronous input can hover between logic levels, how the resolution failure rate falls exponentially with the time allowed, and why buses cannot be crossed one bit at a time.
- 08 Register Retiming: Moving Flip-Flops Across Combinational Logic How a retiming tool redistributes registers along a path without changing the function, what the legal moves are, and why the resulting netlist no longer matches the RTL that was written.
- 09 Equivalence Checking: Proving a Netlist Matches Its RTL How combinational equivalence is reduced to a miter of two circuits and a satisfiability question, why sequential transformations break that reduction, and where the proof stops being cheap.
- 10 High-Level Synthesis: Scheduling, Binding, and the Latency-Area Trade How a C-level description becomes a datapath through dependency scheduling and resource binding, why the loop and array decisions dominate the result, and where the generated hardware diverges from the source.