Hardware Engineering · Cluster
Digital Logic
Gates, flip-flops, and combinational design.
- 01 How a CMOS Gate Computes with Pull-Up and Pull-Down Networks The transistor network behind a static CMOS gate, how the voltage transfer characteristic defines noise margins, and why stack height limits fan-in.
- 02 Canonical Forms, Minterms, and the Cost of Two-Level Logic How any Boolean function is written as a sum of minterms or product of maxterms, and why literal count is the currency that minimization tries to spend.
- 03 Two-Level Minimization with Prime Implicants and the Quine-McCluskey Method How adjacent minterms merge into prime implicants, how don't-care rows change the cover, and why exact minimization becomes intractable past a handful of inputs.
- 04 Combinational Hazards and Why Consensus Terms Eliminate Glitches How unequal path delays produce output pulses in a logically correct circuit, how static and dynamic hazards differ, and when adding redundant logic is the fix.
- 05 Multiplexers, Decoders, and Shannon Expansion as Logic Realization Why a 2-to-1 multiplexer can implement any function once its data inputs are tied to constants, and how decoder-and-OR structures realize sum-of-products forms.
- 06 Latches, Flip-Flops, and What Edge Sensitivity Actually Means How a cross-coupled pair stores a bit, why a master-slave arrangement turns level sensitivity into edge triggering, and what transparency costs downstream.
- 07 Setup and Hold Time, Metastability, and the Two-Flop Synchronizer Why a flip-flop needs its input stable around the clock edge, how a near-threshold sample resolves probabilistically, and how cascaded flops bound the failure rate.
- 08 Clock Skew, Jitter, and the Synchronous Timing Budget The two inequalities that decide whether a synchronous design works, how skew helps setup and hurts hold, and why clock distribution is a first-class design problem.
- 09 State Encoding and Next-State Logic in a Finite-State Machine How the choice between binary, one-hot, and Gray encoding moves cost between flip-flops and decode logic, and why unused encodings are a reliability problem.
- 10 Clock Domain Crossing: Synchronizers, Handshakes, and Asynchronous FIFOs Why a signal crossing between unrelated clocks cannot be checked by static timing, and the three structures that carry data across a boundary safely.