How a CMOS Gate Computes with Pull-Up and Pull-Down Networks

A logic gate is a physical device that must map a continuous input voltage onto one of two output levels with enough margin that the next gate reads it unambiguously. Every abstraction above the gate — Boolean algebra, timing diagrams, synthesis — assumes that mapping holds. Static CMOS achieves it with two complementary networks of transistors, and the shape of the resulting transfer curve explains most of the practical rules about which gates to use.

The switch model and the complementary pair

An n-channel MOSFET conducts between source and drain when its gate is at a high potential relative to the source; a p-channel device conducts when its gate is low. Treating each transistor as a voltage-controlled switch gives a model accurate enough to reason about function, though not about speed.

A static CMOS gate has two networks between the output node and the rails. The pull-up network connects the output to the positive supply and is built only from p-channel devices. The pull-down network connects the output to ground and is built only from n-channel devices. The two networks are dual: wherever the pull-down has a series path, the pull-up has a parallel path, and vice versa.

For a two-input NAND, the pull-down is two n-channel transistors in series, so the output is pulled low only when both inputs are high. The pull-up is two p-channel transistors in parallel, so the output is pulled high when either input is low. For a two-input NOR the arrangement inverts: parallel pull-down, series pull-up.

The complementarity has a consequence that defines the logic family. For every input combination, exactly one network conducts, so there is never a direct path from supply to ground in the steady state. A gate that is not switching dissipates only leakage current. All dynamic power comes from charging and discharging the capacitance of output nodes and wires, which is why the familiar energy expression for a node switched at frequency $f$ is proportional to $C V^2 f$ with an activity factor. Bipolar families such as TTL and ECL burn current continuously and pay for it in static power; CMOS does not.

What the voltage transfer characteristic buys

Plot the output voltage against the input voltage for an inverter and the curve has three regions. At low input the output sits at the supply rail. At high input it sits at ground. In between the curve falls steeply through a narrow transition band, and the point where input equals output is the switching threshold. A symmetric inverter — p-channel device sized to match the weaker hole mobility, roughly two to three times the width of the n-channel device — places that threshold near half the supply.

The steepness of the transition is what makes digital logic viable. Define $V_{IL}$ as the highest input that still reads as a logic zero and $V_{IH}$ as the lowest input that reads as a logic one. Define $V_{OL}$ and $V_{OH}$ as the output levels produced in those states. The low noise margin is $V_{IL} - V_{OL}$ and the high noise margin is $V_{OH} - V_{IH}$. A signal may be corrupted by induced noise, ground bounce, or a resistive drop along a wire up to that margin and still be restored by the receiving gate.

Because a CMOS gate’s output is driven to a rail through a conducting transistor, $V_{OL}$ is close to zero and $V_{OH}$ is close to the supply. That is the property that lets CMOS outputs drive CMOS inputs directly and makes level translation between different supply voltages a separate problem rather than a matter of luck. It also means the margins scale with the supply: at very low supply voltages the transition band does not shrink proportionally, and the ratio of margin to noise degrades.

A gate’s input capacitance is the load its fan-out presents. Each additional input a gate drives adds gate capacitance to the driving node, and the delay of the driver grows approximately linearly with that load in the region where the transistors behave resistively. Fan-out therefore trades directly against speed.

Why NAND is not the mirror of NOR

Functionally, NAND and NOR are duals. Electrically they are not, and the asymmetry is one of the most consequential facts in cell library design.

The pull-up network uses p-channel transistors, whose carrier mobility is roughly half that of electrons in the n-channel device. To achieve comparable resistance, a p-channel transistor must be wider, and wider means more gate capacitance and more area. In a NAND gate the p-channel devices are in parallel: each input sees one device between output and supply. In a NOR gate the p-channel devices are in series, so the pull-up path has two devices in the way, each of them already weak. The result is that a two-input NOR is substantially slower than a two-input NAND built in the same process, and the gap widens with fan-in.

Series connection in the pull-down has a matching cost. Two n-channel transistors in series present roughly twice the resistance of one, so a NAND gate’s fall time is worse than an inverter’s, and a four-input NAND worse still. Stacked devices also suffer from the body effect: the source of an upper device in the stack sits above ground, its threshold rises, and it conducts less strongly for the same gate voltage. Delay through a stack therefore grows faster than the stack height, which is why standard cell libraries stop at modest fan-in and why wide functions are built as trees of smaller gates rather than as one large gate.

Gate	Pull-down	Pull-up	Relative pull-up strength
Inverter	1 device	1 device	baseline
NAND2	2 series	2 parallel	good
NOR2	2 parallel	2 series	poor
AND2	NAND2 + inverter	—	good, extra stage
OR2	NOR2 + inverter	—	poor, extra stage

The table also explains why AND and OR cost more than NAND and NOR: they are the inverting forms followed by an inverter, adding a stage of delay. Synthesis tools therefore map logic to inverting gates and absorb the inversions into the surrounding network, which is why a netlist full of NAND and NOR gates can implement a function written entirely with AND and OR. This is the same transformation that canonical two-level forms make explicit when they convert a sum of products into a NAND-NAND structure.

Pass gates, transmission gates, and where static CMOS ends

Not every gate is a complementary pair. A pass-transistor gate routes a data signal through a transistor controlled by another signal, which is compact but has a defect: an n-channel device passes a strong zero and a weak one, so the high level at the output degrades by roughly a threshold voltage. A transmission gate fixes this by placing an n-channel and a p-channel device in parallel with complementary control, restoring the full rail-to-rail swing at the cost of two transistors and the need to generate both polarities of the control signal.

Multiplexers and XOR structures are frequently built this way because the alternative in static CMOS is expensive. A two-input XOR in a pure complementary implementation needs on the order of a dozen transistors, whereas a transmission-gate version needs fewer and drives a lighter load. The trade-off is that pass-gate structures are harder to test and can produce intermediate levels if the control signals overlap, which is one reason synthesis defaults to static CMOS for anything that must tolerate adverse conditions.

A switch-level model in code

The switch model is simple enough to simulate directly and useful for checking a gate’s structure against its intended truth table. The following evaluates a NAND and a NOR from their network topologies rather than from the operators.

def nand2(a, b):
    # pull-down: series n-channel devices; pull-up: parallel p-channel devices
    pulldown = a and b          # conducts only when both inputs high
    pullup = (not a) or (not b)  # conducts when either input low
    assert not (pulldown and pullup), "both networks on: short circuit"
    return 0 if pulldown else 1


def nor2(a, b):
    pulldown = a or b
    pullup = (not a) and (not b)
    assert not (pulldown and pullup), "both networks on: short circuit"
    return 0 if pulldown else 1


for a in (0, 1):
    for b in (0, 1):
        assert nand2(a, b) == (0 if a and b else 1)
        assert nor2(a, b) == (0 if a or b else 1)

The assertion encodes the structural invariant of static CMOS: the two networks are never conducting at once. It holds for every input combination above, and the proof for an arbitrary gate is the duality of the two networks. A design in which both networks can conduct is a short circuit, and a design in which neither can conduct leaves the output floating — the condition that makes dynamic logic require precharge and evaluation phases.

Failure modes that the switch model hides

Three effects matter in practice and none appear in the Boolean abstraction.

Leakage: a modern process has gate oxide thin enough that tunnelling current flows through the insulator, and subthreshold conduction flows even when a device is nominally off. A large block of idle gates therefore draws current proportional to its transistor count, which is why power gating exists. The switch model says off means off; it does not.

Ratio failures: the model assumes a conducting p-channel device pulls the output all the way to the supply. In a pass-transistor gate or a gate with a very weak pull-up, the output may settle at an intermediate level that a receiving gate interprets differently than intended. Static CMOS avoids this by construction; pseudo-n-channel logic does not, and pays with reduced noise margin.

Charge sharing: when a dynamic node is precharged and several internal nodes are at zero, turning on an evaluation path redistributes charge among them and can drop the output below the threshold of the following inverter. This is a failure of the topology, not of the logic function, and it appears only when internal capacitances are comparable to the output capacitance.

The gate’s job is to make a continuous voltage look discrete. Everything in the rest of this cluster — two-level minimization, hazard analysis, and sequential elements — assumes that job is done correctly.