Clock Skew, Jitter, and the Synchronous Timing Budget

A synchronous design runs correctly when two inequalities hold for every register-to-register path. Neither is about the logic function. Both are about the difference between the moment data leaves the launching register and the moment the capturing register closes. The clock reaches those two registers through a distribution network with finite, uncertain delay, and that uncertainty is subtracted directly from the time available.

The two inequalities

Consider a path from a launching flip-flop $A$ to a capturing flip-flop $B$, both on the same clock. The data leaves $A$ a clock-to-output delay $t_{cq}$ after the edge, propagates through combinational logic with delay bounded by $t_{pd}$, and must be stable at $B$ for a setup interval $t_{su}$ before the next edge.

Define skew as the difference in clock arrival time between the capturing and launching registers, positive when the capture clock arrives later. With a clock period $T$, the setup constraint is

$$t_{cq} + t_{pd} \le T + \text{skew} - t_{su} - t_{\text{jitter}}$$

Positive skew gives the path more time, because the capturing edge arrives later. That is the entire content of “useful skew”: deliberately delaying the clock to a register whose inputs are late is a legitimate way to meet setup, and it is standard practice in clock tree synthesis.

The hold constraint is the same path examined at the minimum delay corner:

$$t_{cq} + t_{pd,min} \ge \text{skew} + t_{h}$$

Time is measured from the same edge, so the data must not arrive so early that it overwrites the value the capturing register was supposed to hold from the previous cycle. Here positive skew hurts: if the capture clock arrives late, the register holds the old value for less time, and a fast path can corrupt it.

The two inequalities pull in opposite directions with respect to skew, which is the central tension of clock distribution. A design that adds skew to fix setup makes hold harder; the usual resolution is to fix hold violations with local delay insertion rather than with clock skew, and to reserve useful skew for the setup-critical paths where it does not endanger hold.

Note also what the hold inequality does not contain: the clock period. Hold violations are independent of frequency. This is why a design that fails hold cannot be fixed by slowing the clock down, a fact that surprises people who have only met setup failures, and why simulations run at a low frequency can pass while the silicon fails.

Where skew comes from

Skew is not a single number. It is the difference between two arrival times, each of which is a sum of contributions.

Insertion delay is the time from the clock source to a register’s clock pin. In a tree, the delay is the sum of the buffer and wire delays along the path. Two registers at different depths in the tree see different insertion delays, and the difference is skew. Balancing a tree means equalizing insertion delay by construction, which is what a symmetric H-tree does: identical branch lengths at every level mean identical path lengths from root to every leaf, at least before process variation.

Global skew is the difference between the earliest and latest clock arrival anywhere in the design. Local skew is the difference between two registers that actually communicate. Local skew is the one that matters for timing, and it is usually much smaller than global skew, because two nearby registers usually sit under the same subtree.

The clock network is built from buffers, and each buffer adds delay, power, and a source of variation. A tree with many levels has more total insertion delay and more skew sensitivity to device variation; a tree with few levels must drive more capacitance per buffer, so its edges are slower and its short-circuit power is higher. Clock grids avoid skew by shorting many points together, at the cost of driving a large capacitance and burning power continuously.

Jitter is the temporal variation of the clock edge itself, contributed by the oscillator, the phase-locked loop, the supply network, and crosstalk. It is usually split into random jitter, which grows without bound over long intervals, and deterministic jitter from identifiable sources such as supply noise. Because the setup inequality uses the period between two edges, the relevant quantity for a single-cycle path is the cycle-to-cycle jitter rather than the total, and for a path spanning many cycles it is the accumulated jitter over that interval.

Duty-cycle distortion matters when the design uses both clock phases. A path launched on the rising edge and captured on the falling edge has a budget set by the high phase rather than by the period, and if the clock’s high time is short by a few percent, that path loses that fraction of its budget while other paths are unaffected.

The maximum frequency

Rearranging the setup inequality gives the highest frequency at which a path can run:

$$f_{\max} = \frac{1}{t_{cq} + t_{pd} + t_{su} - \text{skew} + t_{\text{jitter}}}$$

The critical path is the one that maximizes the denominator, and it sets the clock period for the whole design. Three observations follow from the form of the expression.

The fixed terms $t_{cq}$ and $t_{su}$ do not shrink with the logic. As processes improve, gate delays fall faster than register setup and clock-to-output times, so the fraction of the period available for logic decreases. This is the mechanism behind the diminishing returns of deeper pipelines: each additional stage adds another pair of fixed overheads.

Splitting a long path in half does not double the frequency, even ignoring those overheads, because the path had a single worst-case delay and dividing it requires a register in the middle with its own constraints. The gain from adding a pipeline stage is bounded by how much of the original delay was logic rather than clock overhead and routing.

Skew and jitter are subtracted from the numerator budget exactly like logic delay, but they cannot be optimized by rewriting the logic. They are properties of the clock network and the supply, and they must be budgeted before the logic is written. A design that spends the entire period on logic and then discovers it has 10 percent of the period left for skew and jitter has no options except reducing the frequency.

def setup_slack(period, t_cq, t_pd, t_su, skew, jitter):
    """Slack of a launch-to-capture path. Positive slack means timing is met."""
    return period + skew - t_su - jitter - (t_cq + t_pd)


def hold_slack(t_cq, t_pd_min, t_h, skew):
    """Hold margin. Note that the clock period does not appear."""
    return (t_cq + t_pd_min) - skew - t_h


# Illustrative numbers for the shape of the trade, not a measurement of any process.
# Note how raising skew adds to setup_slack and subtracts from hold_slack.
for skew in (-0.02, 0.0, 0.02):
    print(round(skew, 3),
          round(setup_slack(1.0, 0.06, 0.80, 0.04, skew, 0.02), 3),
          round(hold_slack(0.06, 0.05, 0.0, skew), 3))

The printed values are arithmetic on the inputs, and they show the direction of the trade: skew moves slack from one check to the other. In a real flow, the numbers come from characterized libraries and extracted parasitics, and the corner is chosen so that the two checks are evaluated at opposite extremes of delay.

Corners, variation, and derating

Setup is checked at the slow corner: slow transistors, low supply, high temperature. Hold is checked at the fast corner: fast transistors, high supply, low temperature. On-chip variation means the two extremes can occur on the same die, so a path’s launch and capture registers may be at different corners, and a conservative analysis derates each end accordingly.

Derating consists of pessimism applied to the model, not to the silicon. A path analysed as if its launching register were slow and its capturing register fast has a less favourable setup margin than it will ever have in reality. The cost of the pessimism is a lower achievable frequency; the alternative is a design whose signoff does not correspond to any analysable condition. The trend in static timing analysis has been to reduce the pessimism — modelling variation statistically rather than as independent worst-case corners — precisely because the conservative approach leaves performance on the table.

The interaction with skew is direct. On-chip variation makes insertion delays uncertain, and the uncertainty enters the timing equations as an additional skew term. A clock tree that is perfectly balanced at the nominal corner is not perfectly balanced at the slow corner, because the buffers along different branches respond differently to the same variation.

Keeping the clock network cheap

The clock network switches every cycle by construction, so its dynamic power is proportional to the capacitance of the entire distribution tree. It is one of the largest single contributors to dynamic power in a synchronous design, and it is unusual in that its activity is not related to the data.

Clock gating is the standard remedy: an enable signal, integrated with a latch so that it can only change while the clock is inactive, gates off the clock to a block that is idle. The latch is essential, because a combinational enable can glitch and produce a runt pulse, which is the failure mode described in combinational hazards.

Multi-domain clocking is the other lever. A design with several clocks at different frequencies lets each block run at the rate its work requires, and the clock network for a slow block is cheaper than the network for a fast one. The cost is that every signal crossing between domains needs a synchronizer, and a design with many domains has many boundaries to verify — the subject of clock domain crossing.

There is also the option of not having a global clock: asynchronous and locally clocked designs avoid the distribution problem entirely, at the cost of a design methodology and a verification story that are substantially harder. The practical position for most synchronous work is that skew must be budgeted, minimized where it matters, and occasionally exploited, and that the budget must be decided before the logic is written, because it cannot be recovered afterwards.