Wafer Probe and the Economics of Test Coverage

Probing is the first point at which a die is measured rather than predicted. Before it, a wafer’s value is the expected yield of the yield model. After it, the wafer carries a map of which sites are good, and every subsequent step — dicing, assembly, packaging, final test — can be applied only to the good ones. That map is worth money because packaging is expensive: the cost of assembling and testing a die that is known to be bad is pure loss, and probe exists to prevent it.

Making contact with the wafer

A probe card is a printed circuit board with an array of fine contacts that press onto the die’s pads. For pad-limited designs the pads sit in a ring or in rows on a pitch set by the die’s perimeter, and the probe needles must match that pitch. As die perimeters have shrunk, probe pitch has followed, and the mechanical tolerance on planarity — how far the tips of the needles deviate from a common plane — is a fraction of the contact’s vertical travel. A card with hundreds or thousands of contacts must have every one land within its pad, with an overtravel of a few tens of micrometres to break through the oxide that grows on an aluminium pad.

Contact resistance is the quantity that determines whether the test is measuring the die or the probe. A fresh tip on a clean pad makes contact in the range of an ohm; an oxidised tip on an oxidised pad can reach tens of ohms, and for a current-carrying supply pin that drop appears as a voltage sag the die sees as a brownout. The standard remedy is to clean the tips at intervals and to verify contact resistance as part of the test setup, and high-current pins use multiple contacts in parallel so that the resistance per pin falls.

The card is also a transmission line for the high-speed pins. A scan chain shifted at tens of megahertz and a functional test at a gigahertz or more both need the impedance from tester to die to be controlled, and a vertical card’s needles are short enough that their inductance and capacitance stay tolerable at those rates. Probe over active circuitry, in which contact is made to pads placed above the functional area rather than in a perimeter ring, exists precisely to keep the needles short and to allow the pad count to grow without growing the die.

What probe measures, and when

Probe test is applied in stages. The first is a contact and continuity check: verify that every supply pin draws current and that every signal pin is neither open nor shorted to a neighbour. This catches gross assembly failures of the probe card itself and gross defects on the wafer, and it costs almost nothing in time because the measurement is a single DC point per pin.

The second stage is parametric: measure the quiescent supply current and the leakage on a few pins, and compare against limits derived from the corner analysis. A die that draws far more than the expected quiescent current at a given temperature has a short or a shorted gate that the functional test would find but only after the expensive pattern set has run. Screening on current first is a time optimisation, because a DC measurement is milliseconds and a scan pattern is tens of milliseconds to seconds.

The third stage is structural: the scan vectors described in Scan Chains and Automatic Test Pattern Generation, plus memory built-in self-test for the arrays. The BIST engine runs on-die at the die’s own clock rate, which removes the tester from the timing path; the tester supplies a clock and a pass/fail line and reads out the failure addresses for repair analysis, which memory redundancy and repair then applies.

The fourth stage is functional or at-speed: run the design at its rated frequency with a pattern that exercises the critical paths. Probe cards commonly cannot supply the power and the signal integrity for full at-speed operation across all pins at once, so at-speed test on a wafer is often limited to a subset of pins or deferred to final test after packaging. This is the key economic asymmetry: every test moved from final test to probe saves the packaging cost of a part that would have failed, but a probe-only test misses the failures caused by the package itself.

The arithmetic of test time and coverage

Test cost is time on a tester multiplied by the tester’s hourly cost, divided by the number of dies tested in parallel. A tester that runs one die at a time at a few seconds per die, with a cost per hour in the tens of dollars, gives a per-die cost of a fraction of a cent to a few cents depending on the vector count. That looks negligible against a packaged part’s price, and it is not, because the comparison is not against the part price but against the marginal yield.

Consider the choice of whether to add a thousand more scan patterns. The added patterns find some additional faulty dies that would otherwise pass probe and be packaged. The saving is the number of such dies times the packaged cost of a part, which is the die cost plus package plus assembly plus final test. The cost is the added test time for every die on the wafer, good and bad. The added patterns are worth it when the escape reduction times the packaged cost exceeds the added time times the tester rate times the number of dies. Since packaged cost is often several times the die cost, and the escape rate reduction from a thousand extra patterns is small in absolute terms but not zero, the trade is usually favourable until the escape rate falls below the point where the additional patterns are chasing faults that no longer exist in the process.

The direction of the trade reverses as a process matures. In a new process, the defect density is high and the marginal patterns find real defects; in a mature one, the remaining escapes are dominated by defects the fault model does not describe, and extra patterns built on that model add time without finding them. Fabs therefore reduce pattern counts on mature products and add new fault models rather than more vectors of the old kind.

There is also a parallel-testing dimension. A probe card that contacts more dies at once amortises the per-die time, but the tester’s pin electronics are a fixed resource, and the number of dies that can be tested simultaneously is limited by the tester’s channel count and power supply capacity. Multi-site testing grows the card’s complexity and its planarity requirement, since the contacts must land on several dies spread across a larger area of the wafer, and the card must tolerate the wafer’s own non-planarity across that span.

Known-good die and the cost of skipping probe

A die that passes probe is not a known-good die in the strict sense. It is a die that passed the tests applied at probe, at the temperature and voltage and frequency those tests used. Whether that is sufficient depends on what happens next. For a plastic package with a few hundred pins, the package adds wire bonds and a moulding step, and the dominant new failure modes are bond failure and die-attach voids, neither of which is exercised by probe. For a multi-die package or a chiplet assembly, the economics change: a bad die discovered after assembly of a large module can require scrapping the whole module, so the value of a more thorough probe rises with the value of the assembly it feeds, and the requirements are those set out in Known-Good-Die and the Trust Problem in Multi-Die Assembly.

The extreme case is a wafer-to-wafer bonded stack, where the dies cannot be separated after bonding and a single bad die destroys the pair. In that case the probe must approach the coverage of final test, including at-speed operation, and the probe card must contact every die on the wafer rather than a sample. The economics then favour dies with built-in self-test that runs at speed on-die, because the tester’s own timing accuracy is not available through a probe card at the rates the die runs.

The opposite case is a discrete device or a small analogue part, where the package is a few cents and final test can cover what probe skips. There the probe is a coarse screen, sometimes a sample rather than a full wafer, and the cost model is entirely different: the goal is to avoid packaging the obviously dead, not to guarantee a good part.

Where probe yield and final-test yield diverge

A large fraction of probe failures are not defects. They are marginal parametric results caused by contact resistance, by temperature differences between the probe environment and the final-test socket, or by the tester’s own measurement uncertainty. The standard diagnostic is to re-probe the failing dies; a die that passes on the second touch was a contact problem, and a die that fails twice is real. The rate of such first-pass failures is a card-quality metric, and a card whose contact resistance drifts over a wafer’s worth of touchdowns produces a radial pattern of failures that tracks the order of contact rather than the die’s position.

Temperature is a genuine confound. Probe happens at a controlled wafer temperature, often elevated to accelerate some failure modes and to match the operating environment. A timing failure at high temperature on a fast process corner is a real part failure; a timing failure caused by the die being hotter than intended because the probe environment heats the wafer unevenly is not. The failure maps from a probe are therefore only interpretable alongside the temperature map of the chuck, and fabs that probe at temperature must characterise the chuck’s uniformity rather than assume it.

What probe cannot see is the failures introduced after it. Assembly can crack a die, a bond can have a marginal weld, and the package’s own thermal expansion can cause a stress that only appears after cycling. Those failures land in final test, and their rate sets the floor on how much probe coverage is worth buying: past a point, the escapes are dominated by assembly, and additional wafer-level patterns do not reduce the shipped failure rate at all. Final test also has access the probe card lacks, because the part is in its package with its pins exposed: a die that implements the IEEE 1149.1 test access port can be driven and observed through a boundary register at each pin instead of through a functional vector set. This is the reason the test strategy is designed as a whole, with the split between probe, final test, and burn-in chosen to put each test where it is cheapest to apply while still catching the failure it targets.