Hardware Engineering · Cluster
Manufacturing
Fabrication, yield, and test.
- 01 The Unit Step of Fabrication: Lithography, Etch, and Deposition How one patterned layer is built on a wafer: resist coating, exposure through a reduced reticle, development, etch or implant, and the overlay budget that ties every layer to the one below it.
- 02 Design Rules as an Encoding of Process Limits Why a process rule deck is layer-pair specific, how width, spacing, and enclosure numbers derive from lithography and etch capability, and what a design rule checker can and cannot prove about a layout.
- 03 Process Corners and Why Timing Sign-off Is a Set of Scenarios How transistor speed and interconnect parasitics are bounded by slow, fast, and nominal process corners, temperature, and voltage, and why static timing analysis closes each combination separately.
- 04 Yield Models That Turn Defect Density into Die Cost The Poisson and negative binomial yield formulas, why clustering makes the Poisson model pessimistic, and how die area, redundancy, and wafer size set the cost of a working part.
- 05 Scan Chains and Automatic Test Pattern Generation Why a flip-flop becomes a two-mode scan cell, how a stuck-at fault model turns testing into a search for input patterns, and what the ATPG tool trades away when it cannot fill the vector.
- 06 Wafer Probe and the Economics of Test Coverage How a probe card makes contact with pads a few tens of micrometres wide, why test time is a fab cost, and how the choice of coverage trades probe cost against escape rate and package cost.
- 07 How Power Density and Pin Count Decide the Package How power density, inductance, and thermal expansion decide between wire bond, flip-chip, and wafer-level packaging, and which of the three is usually the binding constraint.
- 08 Memory Redundancy and Repair: Turning Defective Arrays into Working Parts How spare rows and columns, fuse or antifuse programming, and built-in self-repair convert a memory array with dozens of defects into a passing die, and when the spare budget runs out.
- 09 Burn-In, Lifetime Models, and the Bathtub Curve Why a fraction of dies fail early and separately from wear-out, how Arrhenius voltage and temperature acceleration are used to compress a lifetime into a test, and what burn-in costs.
- 10 Known-Good-Die and the Trust Problem in Multi-Die Assembly Why assembling individually working dies does not produce a working module, what a stack test standard can and cannot verify, and what must move on-die to make multi-die packages economical.