The Unit Step of Fabrication: Lithography, Etch, and Deposition

A finished integrated circuit contains no drawn shapes. It contains stacked films of silicon, silicon dioxide, silicon nitride, and metals, each of which was patterned by the same loop of steps repeated dozens of times. Nothing about a transistor is assembled directly; the structure emerges because each pass of the loop removes material where the previous pattern said to, and deposits material where the next pattern will need it. Understanding fabrication means understanding that loop and the error budget that keeps each pass aligned to the ones before it.

The loop, once around

A single pass begins with a clean, prepared surface. The wafer is coated with a light-sensitive polymer, the photoresist, typically by spinning it at a few thousand revolutions per minute to leave a film on the order of a micrometre thick, thinner for the short wavelengths used at critical layers. A soft bake drives off solvent. The resist is then exposed through a photomask, developed in an aqueous base, and baked again to harden the remaining pattern. What is left is a polymer stencil.

Everything after that point is a choice of what to do through the stencil. An etch transfers the pattern into the film beneath by removing the material the resist does not cover. An implant fires dopant ions into exposed silicon, and the resist blocks them elsewhere. A deposition adds a film everywhere and is later patterned by a subsequent pass. A lift-off process deposits metal over resist and dissolves the resist to remove the metal that landed on it. The loop closes with resist stripping and a cleaning step, and the wafer returns to the start, one layer higher.

The ordering constraint is what makes the sequence non-arbitrary. A layer that must be self-aligned to the gate is deposited and etched before the gate is covered by anything else. A contact that must land on a source region is opened after the interlayer dielectric is deposited and planarised, because the dielectric would otherwise have to be etched through a hole whose depth varies with the topography underneath. Each pass therefore leaves the wafer in a state the next pass assumes, and a process integration engineer’s job is largely to keep that assumption true.

Exposure through a reduction reticle

The mask is not the size of the die. Steppers and scanners project the reticle pattern onto the wafer at a reduction ratio, conventionally 4×, so the reticle carries features four times larger than the printed ones and the printed field is one quarter of the reticle in each dimension. A standard field is 26 mm by 33 mm on the wafer, which sets a hard ceiling on die size for a single exposure: a die larger than the field must be stitched from two exposures, with a seam whose overlay error is a permanent yield risk. The reticle itself is a 152 mm square plate whose patterned area is about 104 mm by 132 mm, and it can carry more than one die design, which is how a multi-project wafer shares a single mask set across several products.

Resolution at the critical layers comes from the Rayleigh relation, in which the minimum printable half-pitch scales with wavelength divided by numerical aperture, multiplied by a process factor. Deep-ultraviolet exposure at 193 nm with water immersion, which raises the numerical aperture to about 1.35 because water has a refractive index near 1.44 at that wavelength, reaches half-pitches a small fraction of the wavelength because the aperture is above one and the process factor is pushed toward its practical floor near 0.25.

def half_pitch_nm(wavelength_nm, na, k1):
    return k1 * wavelength_nm / na

def dof_nm(wavelength_nm, na, k2=0.5):
    # depth of focus scales as 1/NA^2, the cost of raising NA
    return k2 * wavelength_nm / (na ** 2)

print(half_pitch_nm(193, 1.35, 0.25))   # ~36 nm
print(dof_nm(193, 1.35))                # ~53 nm

The two lines above state the central trade of lithography: numerical aperture buys resolution and spends depth of focus quadratically. A resist film, an underlying oxide step, and the wafer’s own flatness all consume focus budget, so high-aperture immersion tools require planarised surfaces and thin, uniform resist. The 193 nm wavelength is also absorbed measurably by water and by most polymers, which is why the immersion fluid must be purified and degassed, the gap kept thin, and the resist chemistry, the topcoat, and the fluid treated as one engineering problem rather than three independent choices.

Because the printed image is a diffraction pattern rather than a shadow, the mask data is not a copy of the layout. Optical proximity correction adjusts edge positions and adds sub-resolution assist features that never print but shape the aerial image; the correction is computed against a model of the scanner, so a mask set is specific to a process and a tool type. A design that violates the assumptions baked into that correction, for example by placing a feature at an angle the model handles poorly, prints at a different size than the drawn geometry implies.

Etch, and what the resist actually protects

Reactive ion etching removes material by combining a chemical reaction with ion bombardment. The chemistry supplies selectivity, so that the film to be etched reacts much faster than the resist and the film beneath; the ion flux, directed by the plasma sheath, supplies anisotropy, so that the sidewalls stay near vertical instead of undercutting. Selectivity and anisotropy pull in opposite directions: a highly polymerising chemistry protects sidewalls and improves verticality at the cost of leaving residue at the bottom, and a highly chemical etch clears the bottom but etches laterally.

The consequence is that the resist pattern is not the final dimension. A nominally equal line and space will come out with the line narrower than drawn if the etch consumes some of the resist edge, and the amount depends on the pattern density around the feature because local consumption changes the reactant concentration. Processes therefore specify an etch bias to be added back at mask data prep, and the bias is measured from test structures on a monitor wafer rather than predicted. Overetch, expressed as a percentage of the nominal time, is deliberate: it ensures that films with locally different thickness, for instance over a step, are cleared everywhere, and the cost is that the films not meant to be etched lose some thickness too.

Deposition follows the same pattern of coupled constraints. Chemical vapour deposition gives conformal films that coat sidewalls evenly, which is what a liner needs but what makes a narrow trench hard to fill without a seam. Physical vapour deposition gives directional films with poor sidewall coverage, adequate for a metal seed but not for a high-aspect-ratio feature. Atomic layer deposition grows one saturated monolayer per cycle, giving near-perfect conformality at a throughput cost proportional to film thickness. When a dielectric must be flat before the next layer, chemical mechanical polishing removes topography by combining a mechanical abrasive action with a chemical slurry, and it introduces its own failure modes: dishing of wide metal features and erosion of dense arrays, both of which change the effective thickness that the next lithography step must focus through.

Overlay, the constraint that binds the layers

Every layer after the first must be placed relative to an existing one. Alignment marks etched into the wafer at an earlier pass are located optically, and the scanner corrects translation, rotation, magnification, and several higher-order distortion terms before exposure. What remains is overlay error, and it is budgeted as a fraction of the smallest feature rather than as an absolute distance: a contact that lands outside its target by a larger fraction of the feature size than the enclosure allows becomes an open circuit or a short.

Overlay error accumulates from several independent sources. The scanner contributes stage positioning and lens distortion; the etch contributes a shift if the pattern’s centre of gravity moves during etching; thermal cycles contribute wafer distortion that varies from run to run; and the CMP step contributes local height variation that changes the apparent position of a mark. Because the contributions are independent, the budget is built in quadrature rather than by addition, and each new layer must fit inside a share of the total that shrinks as features shrink. This is why the smallest features are not simply the ones with the best resolution; they are the ones whose enclosure and overlap rules still leave room for the overlay the tool can deliver.

The design rules described in Design Rules as an Encoding of Process Limits are, in effect, the contract that translates this error budget into geometry: minimum enclosure of a contact by the metal around it, minimum extension of a gate beyond the diffusion, minimum spacing between two features that are defined at different layers.

Where the loop stops being repeatable

Three classes of deviation keep the loop from being deterministic. The first is contamination: a particle landing on the wafer before exposure blocks the resist from clearing, and the resulting defect is a missing hole or a bridged line. Fabs quote a particle specification per wafer pass and a maximum added-particle count per process step, and the yield consequence of a particle is computed from the critical area of the layout, as yield models describe. The second is charging: during plasma etch, exposed conductors collect charge, and if a long metal line connects to a gate, the accumulated charge can exceed the breakdown strength of the thin gate oxide. Antenna rules limit the ratio of conductor area to gate area connected during each metal step, and the fix is a diode or a jumper to a higher metal layer that breaks the path.

The third is statistical process drift. Dopant concentrations, film thicknesses, and etched dimensions all vary between wafers and across a wafer, and the variation is not small: a gate length specified at a few tens of nanometres varies by a nanometre or two across the field, which is several percent of the dimension and a much larger fraction of the electrical behaviour. That spread is not a defect in the loop; it is a property of it, and it is why designs are signed off at the corners discussed in Process Corners and Why Timing Sign-off Is a Set of Scenarios rather than at nominal values.

The loop is also slow. A wafer spends weeks in a fab, moving through hundreds of process steps and queueing between them, and the number of masking layers in a modern logic process is on the order of several dozen. Cycle time is therefore a first-order economic quantity: a fab holds work in progress worth millions of dollars, and every additional pass of the loop costs both the tool time for that pass and the yield risk of another chance to introduce a defect. This is the reason process integration favours steps that do two things at once, such as a hardmask that serves as both an etch mask and a CMP stop, and the reason a new process node is qualified layer by layer rather than as a whole.