Design Rules as an Encoding of Process Limits

A process cannot manufacture arbitrary geometry. It can produce features within a range of widths, at spacings above some minimum, with edges that land within a certain distance of where the layout put them, and with a density of material that stays inside a band. A design rule deck is the formal statement of those limits, written as geometric predicates over rectangles and polygons. It exists because the alternative — every design team negotiating with the fab over each layout — does not scale past a handful of designs, and because a rule that is checked by a program can be enforced before a mask is written rather than after a wafer is scrapped.

Rules are about pairs of edges, not about shapes

The naive mental model treats a rule as a property of a shape: a wire must be at least this wide. Most rules are actually constraints on the relationship between two edges, possibly on two different layers. A spacing rule asks how close two edges of the same layer may come. An enclosure rule asks how far an edge of one layer must extend past an edge of another. An overlap rule asks how much two layers must intersect. An extension rule asks how far one layer must protrude beyond a second.

This distinction matters because the same pair of shapes can violate an enclosure rule in one direction and satisfy it in the other. A contact inside a metal pad needs metal on all four sides, and the required amount is often asymmetric: the amount on the side where the next layer’s routing will attach may be larger than the others, because that side must also satisfy a spacing rule to the neighbouring metal. A deck that records enclosure as a single number loses the asymmetry and produces layouts that pass one check and fail a later one.

The other consequence is that rules are indexed by layer pair. There are rules between diffusion and gate, gate and contact, contact and metal, metal and via, via and the next metal, and between a layer and itself. Each pair has a different physical reason, and the numbers differ by more than a factor of two in some cases because the layers are defined by different processes: a diffusion edge is defined by a shallow trench etch, a gate edge by a lithography and etch step at the tightest pitch in the process, and a metal edge by a damascene etch into a dielectric trench.

Where the numbers come from

A minimum width rule comes from the resolution of the lithography step that defines the layer and from the etch’s ability to produce a feature without breaking it up. At the tightest layers, the resolution is close to the printable half-pitch, so the minimum width and the minimum spacing are often the same number and the sum of the two defines the minimum pitch. Pitch is the more fundamental quantity than width, because the lithography process has a minimum period it can print: two features closer than the minimum pitch cannot be resolved as separate, regardless of how narrow each one is.

A minimum spacing rule has a second origin beyond resolution: the gap must be filled and planarised. In a damascene copper process, trenches are etched into a dielectric, filled with barrier and copper, and polished back. A narrow gap between two wide trenches is hard to fill without a void, and the polish step erodes dense arrays differently from isolated lines. Rules therefore distinguish spacing between two wide lines, between two narrow lines, and between a narrow and a wide line, and the wide-to-wide case is usually the most restrictive. Minimum area rules exist for the inverse reason: a metal shape below some area can be lifted off or over-polished, and its resistance becomes dominated by edge effects.

# A minimal rule check: spacing between edges of one layer, expressed as
# rectangles in nanometres. Real decks operate on polygons with all-angle
# edges; this restricted form is enough to show the predicate.
def spacing_ok(a, b, minimum):
    ax0, ay0, ax1, ay1 = a
    bx0, by0, bx1, by1 = b
    dx = max(bx0 - ax1, ax0 - bx1, 0)
    dy = max(by0 - ay1, ay0 - by1, 0)
    return (dx * dx + dy * dy) ** 0.5 >= minimum

print(spacing_ok((0, 0, 100, 50), (130, 0, 200, 50), 40))   # False: gap is 30
print(spacing_ok((0, 0, 100, 50), (140, 0, 200, 50), 40))   # True: gap is 40

Enclosure numbers come from the overlay budget. If a contact must be enclosed by metal on all sides, the enclosure must exceed the worst-case misalignment between the contact layer and the metal layer, plus the amount by which the metal edge may pull back during etch. Overlay is quoted as a fraction of the minimum feature and as an absolute figure; the enclosure rule is set so that even at the worst-case misalignment, some metal remains around the contact. This is why enclosure rules shrink more slowly than width rules as a process advances: the lithography resolution improves faster than the mechanical alignment of one layer to another. The overlay residual that the enclosure rule absorbs is also one of the terms that the sign-off analysis must account for, since a misaligned layer changes the parasitic capacitance of the structures it forms, as Process Corners and Why Timing Sign-off Is a Set of Scenarios describes.

Density rules are the least geometric and the most process-specific. Chemical mechanical polishing removes material at a rate that depends on the local pattern density, so a region with no metal polishes down further than a region full of it. A maximum density rule caps how much of a window may be covered; a minimum density rule forces fill shapes into empty regions. Both are expressed over a sliding window whose size matches the polishing pad’s contact scale, typically tens to hundreds of micrometres, and the fill shapes inserted to satisfy the minimum are themselves design objects that must satisfy spacing and width rules.

What the checker proves

A design rule checker walks the layout, builds a geometric representation of each layer, and evaluates every rule as a predicate over pairs or small groups of shapes. The output is a set of violations with coordinates, and the design is clean when the set is empty. That is a proof about geometry and nothing else.

It does not prove that the circuit works. A layout can satisfy every spacing rule and still have a wire that is too resistive for its driver, a clock net with excessive skew, or a transistor whose drawn width is correct but whose neighbourhood causes the printed width to differ. It does not prove that the mask is manufacturable in the sense of printing with adequate process window; the rules are a conservative approximation of that, and the model-based verification that checks the actual aerial image is a separate step. And it does not prove that the layout matches the schematic: the layout-versus-schematic check is a different program comparing extracted devices and connectivity against a netlist.

There is also the question of which rules are checked. A deck has a recommended set and a required set, and the required set is what the fab will enforce before accepting a mask set. Rules marked recommended affect yield but do not cause rejection. A design that meets only the required set is legal; whether it is economical is a separate judgement, and the difference shows up in the defect density and in the parametric spread, which yield models convert into cost.

The checker’s own correctness is an issue. Decks are code, they are versioned, and a deck bug that misses a class of violations is discovered when a design that passed fails in silicon. Fabs therefore publish deck revision histories and require designs to be checked against a specific revision, and the revision is recorded alongside the mask data. A violation that appears only in a newer deck is a real risk to a design that was already taped out, and it is common for a fab to waive newly introduced rules for designs already released to manufacturing rather than force a respin.

Restricted layouts and the retreat from general geometry

As pitches approach the resolution limit, the set of shapes that print well shrinks faster than the set of shapes that can be drawn. A process may print a perfectly straight line at the minimum width and also print a line that turns a corner, but not print the corner with the same fidelity, and the corner’s rounding consumes the spacing budget to its neighbour. One response is to keep the general rule deck and add many more context-dependent rules; the other is to restrict the allowed geometry so that the rules become simple again.

The restricted approach fixes the pitch of a layer to a small set of allowed values and requires all shapes on that layer to be unidirectional. Routing then happens on one layer in one direction and on the next layer in the orthogonal direction, with vias connecting them. Because every shape on a layer has the same orientation and one of a few widths, the number of distinct geometric contexts collapses, and the lithography for that layer can be optimised for exactly those contexts. The cost is paid by the router: unidirectional layers remove the freedom to jog a wire sideways, so a connection that would have taken one bend may need two or three, and the number of vias rises. Such a design also loses the ability to turn a wire through ninety degrees within a layer, so the router’s remaining degree of freedom at a corner is which layer to change to.

The trade is visible in the rules themselves. A restricted deck has fewer rules with sharper numbers; a general deck has many rules, some of them conditional on neighbourhood, and the conditional ones are where layout engineers spend their time. Both encode the same physics. The difference is whether the design side absorbs the complexity or the mask and verification side does.

Rules as a contract with a version

The rule deck is not a property of the process alone. It is negotiated between what the process can do and what designs need, and it changes when either side changes. A foundry may add a rule because a customer’s layout exposed a failure mode, or relax one because a new lithography illumination mode widened the process window for a particular pattern. Designs are therefore tied to a process flavour and a deck revision, and the tie is not cosmetic: two decks for the same nominal process can differ in the minimum spacing of a mid-level metal by a few nanometres, which changes the routing capacity and therefore the achievable area.

For a designer, the practical consequence is that the rules in a process design kit should be read as the fab’s current best statement of what it will accept, not as a physical law. They are the compressed form of everything the fab knows about printing, etching, polishing, and aligning that particular stack, and they are the only part of that knowledge a layout tool can consume.