Process Corners and Why Timing Sign-off Is a Set of Scenarios

A transistor does not have a delay. It has a delay distribution, and the width of that distribution depends on how the fab ran on the day the wafer was made and where on the wafer the die sat. Sign-off timing cannot work with a distribution directly; static timing analysis is a propagation of numbers through a graph, and it needs a bounded number of them. The corners are the chosen extremes of that distribution, and the scenario set is the enumeration of corners that the analysis must pass.

What varies, and in which direction

Two device parameters dominate. The threshold voltage sets how much gate overdrive exists at the supply voltage, and the effective channel length sets how much current flows for that overdrive. Both are set by process steps with real spread: the gate etch determines length to within some nanometres, and the dopant profile that sets threshold varies with implant dose and with the thermal budget the wafer has seen.

Shorter channels, lower thresholds, and higher mobility all make a transistor faster. A wafer that came out with short channels and low thresholds switches faster and also leaks more; a wafer with long channels and high thresholds switches slower and leaks less. The spread originates in the process steps themselves, each with its own control limits, as the unit process loop sets them. This is a positive correlation between speed and leakage, and it is why the fast corner is not automatically the safe corner for power, and the slow corner is not automatically safe for hold time. The correlation is not perfect, because threshold and length are influenced by partly independent process steps, which is why modern corners are not a single scalar but a joint selection of device parameters.

Interconnect varies independently. Metal and dielectric thicknesses set resistance and capacitance, and the two do not track together: a thick metal layer is lower resistance and, with a fixed dielectric thickness, higher capacitance to its neighbours. Dielectric thickness is itself a process variable. Long global wires also show cross-die variation in a way that devices do not, because the wire spans more of the wafer and sees a larger fraction of the across-wafer gradient.

Temperature enters from the operating environment, not the process, and it does not push in one direction. At low supply voltage, near or below the threshold, a hotter die reduces the threshold and the transistor gets faster, so the delay peak sits at low temperature. At high supply voltage, hotter means more phonon scattering and lower mobility, so the peak sits at high temperature. A sign-off set therefore includes both a low-temperature and a high-temperature case, because a single “worst temperature” does not exist.

Supply voltage enters from the power delivery network. A die sees less than the nominal supply because of IR drop through package and on-die resistance, and the drop depends on activity, so the timing analysis must be run at a reduced voltage that reflects the drop the switching circuit itself causes. Since lower voltage means longer delay, the voltage corner is the lowest voltage the design must tolerate, not the nominal one.

Corner naming convention (illustrative, not a vendor table):

  SS  slow n, slow p      slow devices
  FF  fast n, fast p      fast devices
  SF  slow n, fast p      asymmetric: fast pull-up, slow pull-down
  FS  fast n, slow p      asymmetric: slow pull-up, fast pull-down

  combined with:  supply (low / nominal / high)
                  temperature (low / nominal / high)
                  RC extraction (min / typical / max, plus cross-die)

Why the extremes are not enough

The obvious approach is to analyse each extreme condition and take the worst result. That fails because n-channel and p-channel devices are not perfectly correlated. They are formed by separate implants and are affected by different steps, so the joint distribution of the two contains combinations that a pair of uniform extremes does not represent, and a path’s delay is a weighted sum over stages whose sensitivity to each polarity differs. The combination that is worst for a given path can therefore be one where the two polarities move in opposite directions rather than one where both are extreme in the same direction. A path that mixes logic styles, or one whose load is dominated by interconnect, can likewise have its worst case at a mixed corner rather than at a uniform slow corner.

This is the reason for skew or asymmetric corners, in which n-channel and p-channel devices are drawn from opposite ends of their distributions. A path whose critical transition is a rising edge is sensitive to the p-channel strength; one whose critical transition is falling is sensitive to the n-channel strength. The SF and FS combinations capture the case where one polarity is slow and the other is fast, which a uniform SS corner does not.

On-chip variation adds a second axis. Two transistors a few micrometres apart see almost the same process, but two transistors at opposite corners of the die do not. The spatial correlation is modelled as a random component plus a die-to-die component plus a systematic across-die component, often with a distance-based model: the variance of the difference between two devices grows with their separation. Sign-off handles this either by derating delays with a global factor applied when comparing launch and capture paths, or by characterising the library at multiple corners and selecting launch and capture values from different corners in the same analysis, which is the basis of what is conventionally called path-based analysis of on-chip variation.

The difference matters for hold checks as much as for setup. A setup check compares a launch path with a capture path, and its worst case is a slow launch with a fast capture. A hold check has the opposite sense, and its worst case is a fast launch with a slow capture. A single corner cannot serve both, which is why a full sign-off scenario set roughly doubles: every setup scenario implies a corresponding hold scenario with the roles reversed.

The scenario set is a cost budget

Each scenario costs a full timing analysis over the whole design at every extraction corner. On a large design the number of clock domains, mode combinations, and voltage islands multiplies the set further: a design with several power domains may have a distinct set of scenarios for each mode, because in one mode a domain is on and in another it is off, and the paths that exist differ.

Reducing the set without losing coverage is therefore a real engineering activity. The common techniques are removal of scenarios whose result cannot be worst, which requires an argument about monotonicity that holds for that design; grouping of modes that constrain the same paths; and the use of graph-based analysis for early exploration followed by path-based analysis on the paths that matter, which trades pessimism for runtime. Pessimism is the currency here: graph-based analysis considers the worst possible combination of every gate’s delay along a path simultaneously, which no single die can realise, so it reports paths that fail and would pass on silicon.

Interconnect extraction corners

Parasitics are extracted from layout geometry and assigned a process corner. The combinations are not independent: a metal layer that is thicker than nominal is likely to have a dielectric that is also off nominal in a particular direction, because the two come from different steps and the process control couples them weakly. Extraction decks therefore pair resistance and capacitance extremes into a small number of named cases, such as minimum resistance with maximum capacitance and the reverse, and the timing tool runs each.

The worst case for delay on a long net is maximum resistance with maximum capacitance. The worst case for crosstalk and for coupling noise is maximum capacitance to a neighbouring aggressor, which is not the same combination. A shield or a wide spacing on the most timing-critical nets removes the recovery from that net but spends routing resource, and the decision is made by looking at how much of the timing slack is consumed by the difference between extraction corners rather than by the logic.

Cross-die variation on interconnect is handled by an additional adjustment: because a wire can run from a corner of the die to the opposite corner, the extracted resistance of a long net can be increased by a factor before use, or the same effect can be produced by selecting launch and capture corners that differ. Both approaches are approximations of a continuous spatial gradient, and both are calibrated against the foundry’s measured data for the process.

Where the corner set becomes the process

The number of corners in a sign-off set is a statement about how well the process is controlled. A mature process with tight distributions needs fewer scenarios, because the extremes are close to nominal and the mixed combinations add little. A new process needs more, because the distributions are wide and the correlations between device parameters are less well characterised. The foundry’s corner models are thus a deliverable of the same kind as the design rules: they encode what the fab knows about its own variation, in a form the design tools can consume.

The sign-off is also the place where a manufacturing decision becomes a design decision. Choosing to qualify at a tighter corner set accepts a higher risk of a part that fails at the edge of the distribution; choosing a wider set spends area on buffering and on margin that reduces the achievable frequency. That trade is settled between the product’s reliability requirement and the fab’s yield, and it lands in the corner table that yield models assume when they compute how many dies are good.