Multiphase Buck Converters and Where Regulator Efficiency Goes

A single buck converter large enough to supply a hundred amperes is a poor fit for a processor rail for three reasons: its inductor must be physically large to keep ripple current within bounds, its switching devices must carry the full load current, and its transient response is limited by how fast one inductor’s current can change. Splitting the same job across several identical converters operating in parallel, with their switching instants staggered evenly across the period, addresses all three at once. The arrangement is the standard voltage regulator for any load above a few tens of amperes.

A buck converter in one paragraph

A buck converter chops the input voltage with two switches and a series inductor. When the high-side switch conducts, the inductor sees the difference between input and output and its current ramps up; when the low-side switch conducts, the inductor sees the negative of the output voltage and its current ramps down. The average output equals the input multiplied by the duty cycle $D$ in continuous conduction, and the current ripple is

$$\Delta I = \frac{(V_{\text{in}} - V_{\text{out}}) , D}{L , f_{\text{sw}}}$$

with $f_{\text{sw}}$ the switching frequency. The ripple falls with larger inductance and higher frequency, and both cost something: a larger inductor has more copper loss and slower current slew, and a higher switching frequency increases the switching loss in the FETs and the core loss in the inductor.

The duty cycle is the reason the input voltage matters so much, and the 12 V that feeds it is itself the output of the upstream conversion chain. Converting 12 V to 1 V requires $D \approx 0.083$: the high-side switch is on for about 8 percent of each period. The low-side switch conducts for the other 92 percent and carries most of the conduction loss, which is why synchronous buck designs use a low-side device with very low on-resistance. It also means the high-side switch has very little time to turn on and off, so its switching loss is set by edge rates that must be fast relative to an already short on-time.

Why phases are interleaved rather than merely paralleled

Two converters in parallel with synchronized switching behave exactly like one converter with twice the inductor and twice the silicon: no advantage beyond spreading heat. Staggering their switching instants by half a period changes the picture. Each phase’s inductor current has the same triangular ripple, but the ripple of one phase is rising while the other’s is falling, so the sum at the output has a smaller ripple than either individual current.

With $N$ phases staggered by $2\pi/N$, the ripple of the summed current cancels at harmonics that are multiples of $N$ times the switching frequency, and the residual ripple is roughly $1/N$ of a single phase’s for the same total inductance. Two consequences follow. The output capacitance needed to hold the ripple specification falls by a similar factor, and the per-phase inductance can be smaller, which improves transient response. In effect the converter behaves like a single converter switching at $N f_{\text{sw}}$ for the purpose of output ripple, while each FET still switches at $f_{\text{sw}}$ and therefore incurs switching loss at $f_{\text{sw}}$.

The interleaving angle is not free. Phase timing must be accurate to a small fraction of the period, because a timing error between phases reduces the cancellation; and the phases must share current equally, which requires either droop-based sharing or an explicit current-balance loop. A phase that carries more than its share runs hotter, and because on-resistance rises with temperature, the imbalance grows: the hotter phase carries more current, dissipates more, and gets hotter still. Current-sharing accuracy is therefore a thermal-stability requirement, not just an efficiency one.

The loss terms, in order of size

Conduction loss in the FETs is the dominant term at high load. Each phase’s high-side device conducts for a fraction $D$ of the period and the low-side for $1-D$, so the per-phase conduction loss is approximately $I_{\text{phase}}^2 (D R_{\text{on,hs}} + (1-D) R_{\text{on,ls}})$ plus the inductor’s winding resistance. Because it scales with the square of current, duplicating a single-phase design into $N$ phases divides the total conduction loss by $N$: each phase carries $1/N$ of the current, so its own loss falls by $N^2$, and the $N$ phases together fall by $N$. That saving is bought with silicon, since the $N$ stages together use $N$ times the device area; on a fixed silicon budget the phase count changes the ripple and the transient response but leaves the total conduction loss unchanged.

Switching loss is proportional to $f_{\text{sw}}$, to the input voltage, and to the current being commutated, and it does not fall with phase count. Each phase switches the same voltage and carries $1/N$ of the current, so total switching loss stays roughly constant as phases are added. The trade is therefore between conduction loss, which falls with $N$, and the fixed cost of more phases: more gate drive, more control overhead, more board area, and switching loss that stays flat as the phase count rises.

Inductor core loss scales with the peak-to-peak flux swing and the frequency, and inductor copper loss with the RMS current. Gate drive loss is small but nonzero, and the controller’s own quiescent current sets a floor on the power the converter consumes with no load at all.

A worked example makes the scaling concrete. Take 12 V to 1.0 V at 100 A, four phases, 500 kHz, and 150 nH per phase, all stated as assumed values:

Vin, Vout, Iout = 12.0, 1.0, 100.0
N, fsw, L = 4, 500e3, 150e-9
D = Vout / Vin
Iph = Iout / N
ripple = (Vin - Vout) * D / (L * fsw)
print(f"duty {D:.3f}  per-phase current {Iph:.1f} A")
print(f"per-phase ripple {ripple:.1f} A  ({ripple/Iph*100:.0f}% of phase current)")

With those numbers the per-phase ripple is about half the per-phase average current, which is why the summed ripple at the output stays small while each inductor still carries a large triangular swing. The inductor must be sized for the peak, not the average: saturation current must exceed $I_{\text{phase}} + \Delta I/2$, and the copper must carry the RMS value, which is higher than the average by a factor that depends on the ripple ratio.

Efficiency is a curve with a peak, and the peak moves

A converter’s efficiency at full load is one number; its efficiency at 5 percent load is another, and the second is usually much worse. At light load, conduction loss becomes negligible and the fixed terms dominate: switching loss, gate drive, controller quiescent current, and the core loss of the inductor. A converter optimised for 100 A may be below 50 percent efficient at 2 A.

The standard response is phase shedding: at light load, turn off some phases and let the remaining ones run at a higher per-phase current, which moves them back up the efficiency curve. Shedding is hysteresis-controlled, with a threshold to drop a phase and a lower threshold to bring it back, because a threshold without hysteresis produces oscillation around the boundary. The cost is latency: adding a phase back takes time for its inductor current to ramp and for the loop to rebalance, and during that window the remaining phases carry the whole load.

Dynamic voltage scaling interacts with this. A rail that spends most of its life at 0.7 V and 15 A has a completely different optimum phase count from one that spends its life at 1.1 V and 90 A, and the controller’s phase-shedding thresholds are usually programmed against a model of the expected load profile rather than measured at runtime.

Transient response is set by the inductors, not the silicon

When the load steps, the converter cannot change any inductor’s current instantaneously. Each phase can slew its current at a rate of $(V_{\text{in}} - V_{\text{out}})/L$ when the high-side switch is on, which for 12 V, 1 V, and 150 nH is about 73 A per microsecond per phase. Four phases together can therefore ramp at roughly 290 A/µs in the ideal case where all high-side switches are held on, and less in practice because the controller’s duty-cycle limit and the current-balance loop constrain it.

That slew rate is the reason the output capacitance must supply the load during the first microseconds after a step, and it is why the capacitance and the phases are designed together as one impedance network. The charge needed is the integral of the current deficit, and it is minimised by having many phases with small inductors, which is the same conclusion as the ripple argument but from a different direction. The two objectives conflict at the inductor: small inductance improves transient response and reduces size, while large inductance reduces ripple and conduction loss. Multiphase resolves the conflict by keeping each inductor’s ripple moderate while making the sum small.

Adaptive voltage positioning is the other lever. If the output is allowed to sit slightly high at no load and slightly low at full load, the total voltage window available for a transient is larger, so less capacitance is needed for the same droop. The load line is specified as a slope in milliohms, and the regulator is designed to hit it, which is why a measured rail voltage falls as current rises rather than staying flat. The technique trades DC accuracy for transient headroom, and it is only valid if every load on the rail tolerates the reduced voltage at high current.

Failure modes worth knowing

A phase that fails open leaves the remaining phases to carry the load, and if the controller does not detect it the survivors overheat. A phase that fails short applies the input to the output through the inductor and the low-side switch, which is why a shorted high-side FET is the classic destructive failure in these converters.

Loop instability appears as a low-frequency oscillation of the output, usually at a few kilohertz, and is caused by insufficient phase margin in the compensation. It is dangerous because the average voltage may look correct while the peak excursions violate the load’s limits. Remote sensing makes this worse by adding the sense-line inductance into the loop, and the regulator’s datasheet usually specifies the maximum sense-line length as a stability constraint rather than an accuracy one.

Finally, the current-sense element itself can be the failure. Sensing across the low-side FET’s on-resistance is cheap and lossless but drifts with temperature, since on-resistance rises with temperature; a converter calibrated cold will over-report current when hot, and the overcurrent protection will trip early. Sensing with a dedicated resistor is accurate and stable but costs conduction loss in the main path, which at 100 A is a real fraction of a watt.