Static IR Drop and Dynamic Droop Inside the Die Power Grid

The voltage that matters to a transistor is the voltage between its source and drain at the moment it switches, not the voltage the regulator holds at the socket. Between those two points lie solder bumps, package planes, and a stack of on-die metal layers whose only job is to carry current from a few hundred bump sites to millions of logic cells. That path has resistance, and it has inductance, and both convert the regulator’s clean output into something noticeably worse at the point of use.

The design budget for the difference is called the power integrity budget, and it is split into two parts that behave very differently: a static drop that depends on average current and resistance, and a dynamic droop that depends on how fast the current changes.

The grid is a resistor tree, and the drop is path-dependent

A die’s power grid is a mesh of orthogonal metal stripes on several layers, connected downward by vias. Top layers are thick and wide, carrying current laterally from the bump field toward the middle of the die; lower layers are thin and narrow, feeding individual cells. Current enters at the bumps, spreads through the coarse mesh, and descends through progressively finer meshes to the transistors.

Model the grid as a resistive network and the static drop at any node is the sum of $IR$ products along the path from the nearest bump. The path is not unique, which is the point of the mesh: the current divides according to the conductances, and the drop is found by solving a large sparse linear system with current sources at the cells and voltage sources at the bumps. For a full chip the system has millions of nodes, and the solution is one of the standard full-chip analyses run before tapeout.

Two properties of that solution matter for design. First, the drop is proportional to current density, so a region that draws more current per unit area drops more, and the drop is worst where the local power density is highest and the mesh is thinnest. Second, the drop scales with the square of the distance from a bump for a uniformly loaded plane, because the current accumulated from both sides grows linearly and the resistance grows linearly with distance. Doubling the distance from the nearest bump quadruples the drop for a uniform load. That is why bump placement is a power-integrity decision as much as a package decision, and why dense logic is placed near the bump field rather than at the die edge.

A rough calculation shows the scale. A grid segment 2 µm wide and 1 µm thick in copper has a cross-section of 2 µm² and a resistance of about 8.6 Ω per millimetre at room temperature, so a 100 µm run is 0.86 Ω. Carrying 10 mA through that run drops 8.6 mV; carrying 1 mA drops 0.86 mV. A cell drawing tens of microamps is fine; a cluster of thousands of cells drawing tens of milliamps through a shared narrow segment is not. The budget for the whole grid is typically a few percent of the supply, so on a 0.9 V rail the entire on-die drop may be allowed 20 to 40 mV, and that allowance has to cover millions of parallel paths.

Dynamic droop comes from inductance, not resistance

Current through the grid changes with the workload, and any inductance in the path turns a current change into a voltage excursion: $V = L , di/dt$. The dominant inductance is not on the die, where the loops are short, but in the package and the socket, where the current must travel from board planes to bump field. Package inductance of tens of picohenries to a few hundred picohenries is normal, and a current slew of 1 A per nanosecond through 50 pH produces a 50 mV excursion on top of whatever the resistance contributes.

The inductive term is why the droop waveform has the shape it does. Immediately after a load step, the local decoupling capacitance supplies the current, and the voltage falls as that capacitance discharges. The regulator then ramps its inductor currents, and the current flowing through the package inductance changes, generating a further excursion. The die’s own capacitance and the package inductance form a resonant tank, and the response rings at the tank’s frequency, typically in the tens to low hundreds of megahertz, before settling. The lowest point of that ring is the worst-case voltage the transistors see, and it is what the timing analysis must close against.

The charge required to survive the first droop is the reason on-die decoupling exists; it is the high-frequency end of the same ladder described in decoupling and PDN impedance, and its size follows from the same charge equation used at board level. A 40 A deficit held for 200 ps discharges 8 nC; against a 30 mV allowance that is about 270 nF, which is far more than a die carries, so the package current must arrive much sooner than 200 ps and the real deficit window is tens of picoseconds. The arithmetic is unforgiving, and it is why the on-die capacitance is a first-order design target rather than an afterthought.

Guardbands, and why they are not waste

Timing is analysed at a supply voltage, and if the supply can droop, the analysis must use the lowest voltage the circuit will see while it is switching. The difference between nominal and worst-case is the voltage guardband. It is expensive: delay rises steeply as the supply approaches threshold, so a droop of a few percent of nominal can cost several percent of frequency if the design must close timing at the droop floor rather than at nominal.

The alternative to a fixed guardband is to measure the droop and adapt. Critical-path monitors, replica circuits, and voltage sensors on the die can report the actual droop, and the clock or voltage can be adjusted in response. Adaptive voltage scaling closes the loop between a monitor and the regulator, so the rail is raised when droop is detected rather than always running high enough to cover the worst case. The technique works only if the monitor is representative of the critical paths it protects, and a monitor that is faster or slower than the real critical path either wastes margin or fails to protect it.

A cheaper variant is to design for the droop only where it matters. Cells on paths with large timing slack can tolerate a lower voltage than cells on critical paths, and the grid can be analysed per-region rather than globally. This is the same idea as voltage islands, applied to a droop budget instead of a nominal voltage.

Electromigration sets the current density ceiling

Resistance and inductance set the voltage; electromigration sets the reliability limit. Current flowing through aluminium or copper interconnects drags metal atoms along the electron wind, and at high enough current density the accumulation and depletion of atoms forms voids and hillocks that eventually open or short the wire. The failure is progressive, and its rate depends strongly on current density and temperature.

Black’s equation describes the median time to failure:

$$MTTF = A , J^{-n} , e^{E_a / (k_B T)}$$

where $J$ is current density, $E_a$ the activation energy of the dominant diffusion path, and $n$ an exponent typically between 1 and 2. The exponential in temperature is the severe term: a 10 °C rise roughly halves the lifetime for an activation energy near 0.7 eV, and copper’s activation energy depends on the liner and the surface treatment. Current density enters with an exponent near 2, so halving the current density in a wire multiplies its life by roughly four.

The practical consequence is a current-density limit per unit of metal width, usually specified as an average current for a given cross-section and a separate, higher limit for short pulses. Power grids are sized to stay under those limits everywhere, which is why the top metal layers are thick: a grid that met the IR-drop budget with thin wires would fail the electromigration check at the same current. Via arrays are checked separately, because a via carries the current of the wire above it through a much smaller cross-section and is usually the first thing to fail.

Bidirectional current makes this worse. A grid that carries current from the bumps outward in one region and inward in another has wires whose current reverses with the workload, and electromigration damage is not symmetric with direction; the same wire can accumulate damage from both directions. Designs usually assign a preferred current direction per layer and check the resulting net flux rather than the peak.

The interactions that make this hard

The three effects are not independent. Higher temperature raises resistance, which increases the static drop; it also accelerates electromigration, which lowers the current density the grid can carry. A grid designed at a nominal temperature with a fixed current density therefore loses margin as the die heats, and the loss is concentrated exactly where the current is highest.

The grid also competes with signal routing for metal, and the current it carries is set upstream by the conversion stages that decide how much current the package must pass at what voltage. Every layer given to the power mesh is unavailable for wires, and the trade is made per layer: the top two or three layers are usually dominated by power, the middle layers are mixed, and the lowest layers are almost entirely signal. That allocation is why the drop is worst in the fine-grained mesh near the cells, where the wires are thinnest and the current per wire is set by how many cells share it.

Finally, the analysis is statistical because the current is not known exactly. Switching activity depends on the workload, and the worst-case vector that maximises droop is not the same vector that maximises power or delay. Designs use vectorless estimates, activity propagation from simulation, and a margin for the difference between the two, and the margin is one of the largest single uncertainties in the power-integrity signoff.