Decoupling Capacitors and the Impedance of a Power Distribution Network

A regulator’s control loop has a bandwidth. It measures the output, compares it to a reference, and adjusts a switch or a pass element, and the whole cycle takes time set by the switching frequency and the loop compensation. Anything the load does faster than that bandwidth is invisible to the regulator until it has already happened. A core that goes from idle to full activity in a few hundred picoseconds is faster than any practical loop, so for the first tens of nanoseconds after a load step the supply voltage is set by whatever charge is stored locally, not by the converter.

That is the job of the decoupling network, and the way to specify it is as an impedance.

The target impedance, derived from one load step

Suppose a rail is 1.0 V and the load can step by 40 A. Suppose the specification allows the voltage at the die to fall by 45 mV during that step. The network between the regulator’s sense point and the load must then present an impedance no greater than

$$Z_{\text{target}} = \frac{\Delta V}{\Delta I} = \frac{45\ \text{mV}}{40\ \text{A}} \approx 1.1\ \text{m}\Omega$$

at every frequency where the load current has energy. The number is small enough to be surprising: a milliohm is the resistance of only a few millimetres of copper plane a millimetre wide, and it is well below the ESR of most capacitors. The conclusion follows immediately: no single component can meet the target, because each real capacitor has an equivalent series resistance and inductance that dominate in different frequency ranges. The network has to be built from parts that cover different decades, and the design problem is making the pieces overlap without gaps.

The frequency range matters as much as the value. A load step with a rise time of 100 ps has spectral content up to a few gigahertz; a step lasting 1 µs has content only up to a few hundred kilohertz. Above a few hundred megahertz, the inductance of the die’s own power grid dominates and no board-level capacitor can help, which is why the on-die and in-package capacitance is part of the same accounting.

What a real capacitor looks like

An ideal capacitor has impedance that falls as $1/(2\pi f C)$ forever. A real one is a series RLC: the ceramic body’s capacitance, the metal terminations and solder joints’ resistance, and the loop area of the current path’s inductance. Its impedance falls with frequency until it reaches the series resonance at $f_0 = 1/(2\pi\sqrt{LC})$, where the impedance equals the ESR, and then rises again at 20 dB per decade as the inductance takes over.

The consequence is that a capacitor only behaves like a capacitor in a band around its self-resonant frequency. A large 100 µF part with a nanohenry of ESL resonates in the hundreds of kilohertz and is inductive everywhere above that; a 100 nF part with a quarter of a nanohenry of mounting inductance resonates around thirty megahertz. The band where each part is useful is roughly one decade wide on either side of resonance.

Mounting inductance is usually the limiting term, not the component. A capacitor in a small surface-mount package contributes its own body inductance, but the via pair connecting it to the planes contributes more, and the loop area of the connection sets both. Two vias placed close together, with the current flowing up one and down the other, enclose a small loop; two vias at opposite ends of the part enclose a large one. This is why layout guidance for decoupling is dominated by via placement rather than by capacitor selection: the part is chosen for its capacitance and ESR, but the inductance is chosen by the layout.

Building a flat impedance across four decades

The classical construction is a ladder of decades. Bulk capacitance near the regulator handles the millisecond and microsecond timescales: electrolytic or polymer parts in the hundreds of microfarads, with enough ESR to damp the resonance against the plane inductance. Ceramic parts in the microfarad range handle the tens of microseconds. Smaller ceramics in the hundreds of nanofarads handle the hundreds of nanoseconds, and the on-package and on-die capacitance covers the last decade before the grid’s own inductance takes over.

The number of parts is set by the current each must supply for the time it must supply it, and the current is ultimately supplied by the regulator phases once their loop catches up. If the regulator responds within 1 µs and the load steps by 40 A, then during that microsecond the capacitors must deliver 40 µC. With a 45 mV allowable droop, the required capacitance is

$$C = \frac{I \cdot \Delta t}{\Delta V} = \frac{40\ \text{A} \times 1\ \mu\text{s}}{45\ \text{mV}} \approx 900\ \mu\text{F}$$

which explains why bulk capacitance is measured in hundreds of microfarads and why a single 10 µF ceramic is not a substitute for it, however good its high-frequency behaviour. The same calculation repeated for a 10 ns window gives 9 µF, and for a 100 ps window gives about 90 nF. Each timescale has its own capacitance, and the ladder is the answer to the sequence of windows.

def bulk_capacitance(i_step, t_window, dv_allowed):
    """Charge needed during a load step, before the regulator responds."""
    return i_step * t_window / dv_allowed

for t in (1e-6, 100e-9, 10e-9, 100e-12):
    c = bulk_capacitance(40.0, t, 0.045)
    print(f"{t*1e9:8.0f} ns  ->  {c*1e6:9.2f} uF")

The printed values fall by an order of magnitude per decade of time, which is exactly the ladder.

Anti-resonance between two capacitor values

The ladder has a defect that a single-value design does not. Two parallel capacitors with different self-resonant frequencies form a parallel resonant circuit between them: below the lower resonance both are capacitive, above the higher one both are inductive, and between the two one is capacitive and one inductive, so the pair resonates. At that frequency the impedance of the pair rises sharply, potentially above the target even though each part individually meets it.

The peak is set by the damping, which in a power network is mostly ESR and the loss in the planes. This is why a design with many values of ceramic capacitor can measure worse than a design with a single value: the extra values buy lower impedance in their own bands and create new peaks between the bands. Practical designs attack this three ways. They choose values a decade apart rather than clustered, so the peaks land where the load spectrum is weak. They add a deliberately lossy part, such as a polymer capacitor with a controlled ESR, to damp the peaks. And they rely on the fact that the planes themselves have distributed resistance and inductance, which spreads the resonance rather than leaving it as a single spike.

The measured curve of a real network is therefore not the smooth envelope of the individual parts but a sequence of dips at each resonance and peaks between them. Meeting a target impedance means every peak, not just the average, must stay under the line.

Where the network ends and the die begins

Board-level decoupling stops being effective at the frequency where the package’s own inductance dominates. The current path from the board planes through the socket, the package substrate, and the solder bumps to the die has an inductance that is fixed by geometry, typically in the range of tens to a few hundred picohenries depending on the package. At high frequency that inductance is the impedance, and no amount of board capacitance changes it.

The remaining charge has to come from inside the package: the package’s embedded capacitors, the die’s own decoupling capacitance formed by the non-switching transistors and the wire capacitance of the grid, and the intentional thin-oxide decap cells placed under the power grid. On-die capacitance is limited by area and by leakage, since a thin-oxide capacitor is also a leaky transistor, and it is the reason IR drop inside the grid is a separate problem from board-level droop. The two mechanisms act at different timescales and are budgeted separately.

The handoff between them is not clean. The package inductance and the on-die capacitance form their own resonant tank, and the droop that results is a ringing at the tank’s frequency, which for typical values lands in the tens to low hundreds of megahertz. That ringing is the “first droop” seen in every power-integrity simulation, and it is the reason a load step produces a waveform that overshoots and oscillates rather than settling monotonically.

Limits of the impedance approach

The target-impedance method treats the network as a linear, time-invariant two-port and the load as a current source. Both assumptions fail at the edges. A processor’s current draw is not a smooth step but a sequence of clock-aligned bursts, so its spectrum has lines rather than a continuous envelope, and a resonance that lands on a line matters more than one that lands between them. The load is also not a fixed current source: at low voltage the transistors’ own behaviour changes, and the current during a droop is lower than the current at nominal, which softens the droop slightly.

The method also ignores the DC path. A network can meet its target impedance at every frequency and still fail because the plane resistance produces a static drop under continuous current, or because a via’s current-carrying capacity is exceeded. Those are separate checks, and the impedance curve is only the AC half of the budget.