The Power Delivery Chain from Wall Adapter to Core Rail

A modern processor core runs at a little under a volt and draws something on the order of a hundred amperes. Those two numbers together describe the whole problem of power delivery: the energy arrives at the board at 12 V, where a hundred amperes would be an absurd current to move through copper, and must be converted down by more than an order of magnitude within a few centimetres of the die. Every stage of that conversion loses a fraction of the power passing through it, and the fractions multiply.

The arithmetic is worth doing before any of the mechanisms, because it explains nearly every layout decision on a motherboard.

Why the core rail is low and the current is high

Dynamic power in CMOS scales with the square of the supply voltage, so a core supplied at 0.9 V rather than 1.8 V dissipates roughly a quarter as much per switching event at the same frequency. That is the entire reason supply voltages fell steadily for two decades: at a fixed power budget, a lower voltage buys either more frequency or more transistors.

The cost is current. Power is the product of voltage and current, so a load that consumes 90 W at 0.9 V draws 100 A, and the same load at 12 V would draw 7.5 A. Since resistive loss in any conductor is $I^2 R$, moving that 100 A through a conductor with 1 mΩ of resistance dissipates 10 W, while moving 7.5 A through the same conductor dissipates about 56 mW. High current is expensive to transport; low voltage is efficient to use. The resolution is to transport at high voltage and convert at the point of use, which is what every stage of the chain does.

The same asymmetry fixes the geometry. A motherboard plane carrying 100 A must be wide, thick, and short, because the resistance of a copper plane falls with width and thickness and rises with length. A 12 V trace carrying 8 A can be narrow. This is why the 12 V input to a socket area arrives on a couple of thick layers while the core rail is a broad copper pour directly under the regulator.

The stages and what each one costs

The chain from the wall has four conversion steps in a typical desktop or server system, and each has a characteristic efficiency.

The AC-to-DC supply rectifies mains and produces a regulated 12 V output, plus 5 V and 3.3 V for peripherals. Its efficiency is quoted at a given load fraction, and the number falls sharply at light load because fixed switching and control losses dominate. An 80 Plus Bronze supply is required to reach 82 percent at 20 percent load, 85 percent at 50 percent, and 82 percent at full load; higher tiers raise those figures by a few points each. The precise thresholds are a certification matter, but the shape of the curve is universal: conversion efficiency peaks somewhere around half load and degrades in both directions.

The 12 V then travels across the board. Loss here is pure $I^2R$ in planes, connectors, and cable, and it is small only because the current is small. A 12 V rail delivering 300 W carries 25 A; at the few milliohms of a connector pair and a short cable run, that is a watt or two.

At the socket, a buck regulator steps 12 V down to the core voltage. This is the stage with the most demanding job, because it must supply a load that changes by tens of amperes in nanoseconds while holding the output within a few tens of millivolts. Its steady-state efficiency is typically in the high eighties to low nineties at moderate load, and it is the subject of multiphase buck conversion.

Finally, the current enters the package and the die through solder bumps and a grid of on-die metal. This last segment has no conversion loss but has substantial resistive loss, and it is where static IR drop becomes a design constraint rather than a nuisance.

The chain multiplies, and so do its losses

Efficiency in series multiplies. A 90 percent supply feeding an 88 percent regulator feeding a distribution network that loses 5 percent delivers about 75 percent of the wall power to the load; a quarter of the input becomes heat somewhere other than the die. That heat still has to leave the chassis, and in a dense system it is often the supply and the regulator, not the processor, that set the thermal budget.

A short calculation makes the sensitivity visible:

stages = {
    "ac_dc_supply": 0.90,   # at the operating load fraction
    "board_and_connectors": 0.99,
    "vrm": 0.88,
    "package_and_grid": 0.95,
}
p = 1.0
for name, eff in stages.items():
    lost = p * (1 - eff)
    p *= eff
    print(f"{name:22s} loss {lost:6.3f} W  cumulative {p:6.3f} W")

The output is not the point; the structure is. Each stage’s loss is proportional to the power entering it, so a point of efficiency gained at the front of the chain is worth more absolute power than the same point gained at the back. It also means that improving the last stage has a hard ceiling: even a lossless regulator cannot recover what the supply already dissipated.

There is a second, less obvious consequence. Because the regulator’s input power is the output power divided by efficiency, a load that draws 100 W from the core rail draws about 114 W from the 12 V rail. Sizing the 12 V connector and the board planes against the die’s power alone leaves the system short by the conversion loss, and that shortfall appears as voltage droop under load rather than as a clean failure.

Sensing, droop, and the difference between the two ends of the wire

A regulator cannot regulate what it does not measure. If the sense line is taken at the regulator’s output terminals, the voltage at the die is lower than the setpoint by the drop across the package and grid, and the difference grows with current. The fix is remote sensing: a dedicated pair of traces from the regulator’s feedback input to the load, carrying almost no current, so that the feedback loop closes on the voltage the load actually sees. Remote sensing converts a load-dependent error into a fixed offset, which the loop then removes.

Remote sensing has its own failure mode. The sense traces are part of the loop, so inductance in them adds phase shift, and a long or poorly routed sense pair turns a stable regulator into an oscillating one. Regulators therefore specify a maximum sense-line length and require the pair to be routed together, away from switching nodes. A broken sense line is worse than a short one: with no feedback the loop drives to its maximum duty cycle, and the load sees the full input voltage.

The same distinction between the two ends of the wire governs the specification. A regulator’s accuracy is quoted at its own sense point, usually as a percentage of setpoint plus a fixed millivolt term, and the budget for everything between that point and the transistor gate is a separate accounting. That second budget is the subject of decoupling and impedance, and it is where the microsecond-scale behaviour of the supply is decided.

Where the model breaks

The chain model above treats each stage as a scalar efficiency at a fixed load, which is a useful fiction and a misleading one at the edges. Efficiency is a curve, not a number, and a system spends most of its life away from the peak. A processor idling at a few watts loads its regulator at a few percent of rating, where switching losses dominate and efficiency can fall by tens of points; the supply’s own standby consumption is then a visible fraction of total draw.

Current sharing between phases, connector contact resistance, and the temperature coefficient of copper all move the losses by tens of percent across the operating range. Copper’s resistivity rises about 0.4 percent per degree Celsius, so a plane that loses 4 W cold loses more when the chassis is warm, and the loss feeds back into the temperature that caused it. That feedback is mild in a plane and severe in a semiconductor, which is why the leakage discussion belongs at the far end of this cluster rather than here.